Semiconductor device and manufacturing method the same

ABSTRACT

An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

TECHNICAL FIELD

The present invention relates to a semiconductor device including anoxide semiconductor and a manufacturing method thereof.

In this specification, a semiconductor device generally means a devicewhich can function by utilizing semiconductor characteristics, and anelectro-optical device, a semiconductor circuit, and an electronicdevice are all semiconductor devices.

BACKGROUND ART

In recent years, a technique for forming a thin film transistor (TFT) byusing a semiconductor thin film (having a thickness of approximatelyseveral nanometers to several hundred nanometers) formed over asubstrate having an insulating surface has attracted attention. Thinfilm transistors are applied to a wide range of electronic devices suchas ICs or electro-optical devices, and prompt development of thin filmtransistors that are to be used as switching elements in image displaydevices, in particular, is being pushed. Indium oxide is an example ofmetal oxides and is used as a light-transmitting electrode materialwhich is necessary for liquid crystal displays and the like.

Some metal oxides have semiconductor characteristics. For example, metaloxides having semiconductor characteristics include tungsten oxide, tinoxide, indium oxide, zinc oxide, and the like. Thin film transistors inwhich a channel formation region is formed using such a metal oxidehaving semiconductor characteristics are already known (Patent Documents1 to 4 and Non-Patent Document 1).

Further, not only single-component oxides but also multi-componentoxides are known as metal oxides. For example, a homologous compound,InGaO₃(ZnO)_(m) (m is natural number) is known as a multi-componentoxide semiconductor containing In, Ga, and Zn (also referred to as anIn—Ga—Zn—O-based oxide) (Non-Patent Documents 2 to 4).

Furthermore, it is confirmed that an oxide semiconductor containing suchan In—Ga—Zn—O-based oxide is applicable to a channel layer of a thinfilm transistor (Patent Document 5 and Non-Patent Documents 5 and 6).

REFERENCES

[Patent Document 1] Japanese Published Patent Application No. S60-198861

[Patent Document 2] Japanese Published Patent Application No. H8-264794

[Patent Document 3] Japanese Translation of PCT InternationalApplication No. H11-505377

[Patent Document 4] Japanese Published Patent Application No.2000-150900

[Patent Document 5] Japanese Published Patent Application No.2004-103957

-   [Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G    Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M.    Wolf, “A ferroelectric transparent thin-film transistor”, Appl.    Phys. Lett., 17 Jun. 1996, Vol. 68 pp. 3650-3652-   [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, “The    Phase Relations in the In₂O₃—Ga₂ZnO₄—ZnO System at 1350° C.”, J.    Solid State Chem., 1991, Vol. 93, pp. 298-315-   [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura,    “Syntheses and Single-Crystal Data of Homologous Compounds,    In₂O₃(ZnO)_(m) (m=3, 4, and 5), InGaO₃(ZnO)₃, and Ga₂O₃(ZnO)_(m)    (m=7, 8, 9, and 16) in the In₂O₃—ZnGa₂O₄—ZnO System”, J. Solid State    Chem., 1995, Vol. 116, pp. 170-178-   [Non-Patent Document 4] M. Nakamura, N. Kimizuka, T. Mohri, and M.    Isobe, “Homologous Series, Synthesis and Crystal Structure of    InFeO₃(ZnO)m (m: natural number) and its Isostructural Compound”,    KOTAI BUTSURI (SOLID STATE PHYSICS), 1993, Vol. 28, No. 5, pp.    317-327-   [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M.    Hirano, and H. Hosono, “Thin-film transistor fabricated in    single-crystalline transparent oxide semiconductor”, SCIENCE, 2003,    Vol. 300, pp. 1269-1272-   [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M.    Hirano, and H. Hosono, “Room-temperature fabrication of transparent    flexible thin-film transistors using amorphous oxide    semiconductors”, NATURE, 2004, Vol. 432 pp. 488-492

DISCLOSURE OF INVENTION

An object is to provide a highly reliable semiconductor device includinga thin film transistor with stable electric characteristics.

In a method for manufacturing a semiconductor device including a thinfilm transistor in which a semiconductor layer including a channelformation region serves as an oxide semiconductor film, heat treatmentfor increasing purity of the oxide semiconductor film and reducingimpurities such as moisture (heat treatment for dehydration ordehydrogenation) is performed. Further, impurities such as moisture,which exist not only in the oxide semiconductor film but also in asource electrode layer, in a drain electrode layer, and in a gateinsulating layer are reduced by performing heat treatment, andimpurities such as moisture, which exist at interfaces between the oxidesemiconductor film and upper and lower films which are in contact withthe oxide semiconductor film, are reduced by performing heat treatment.

An oxide semiconductor layer is formed and an oxide insulating filmserving as a protective film is formed in contact with the oxidesemiconductor layer, and then heat treatment for dehydration ordehydrogenation is performed. Heat treatment is performed under anitrogen atmosphere, an oxygen atmosphere, or an inert gas atmosphere ofa rare gas (argon, helium, or the like), or under reduced pressure at atemperature of higher than or equal to 200° C. and lower than or equalto 700° C., preferably higher than or equal to 350° C. and lower than astrain point of a substrate, whereby the moisture content in the sourceelectrode layer, the drain electrode layer, the gate insulating layer,and the oxide semiconductor film, or the like is reduced. Further, theheat treatment can repair plasma damage which is caused to the oxidesemiconductor layer when the oxide insulating film serving as aprotective film is formed in contact with the oxide semiconductor layer.The heat treatment can reduce variation in electric characteristics of athin film transistor.

When the oxide semiconductor layer in which the moisture content or thelike is reduced by the heat treatment and whose plasma damage isrepaired is used, electric characteristics of a thin film transistor areimproved and a thin film transistor with mass productivity and highperformance is realized.

In this specification, heat treatment under a nitrogen atmosphere, anoxygen atmosphere, or an inert gas atmosphere of a rare gas (argon,helium, or the like), or under reduced pressure is referred to as heattreatment for dehydration or dehydrogenation. In this specification,“dehydrogenation” does not indicate elimination of only H₂ by the heattreatment. For convenience in this description, elimination of H, OH,and the like is referred to as “dehydrogenation or dehydration”.

Note that the oxide insulating film serving as a protective film whichis in contact with the oxide semiconductor layer is formed using aninorganic insulating film which blocks impurities such as moisture,hydrogen ions, and OH⁻. Typically, a silicon oxide film, a siliconnitride oxide film, an aluminum oxide film, or an aluminum oxynitridefilm is used. In addition, a silicon nitride film or an aluminum nitridefilm may be stacked over the oxide insulating film.

One embodiment of the present invention disclosed in this specificationis a method for manufacturing a semiconductor device including the stepsof: forming a gate electrode layer including a heat resistant conductivematerial; forming a gate insulating layer over the gate electrode layer;forming an oxide semiconductor layer over the gate insulating layer;forming a connection electrode layer, a source electrode layer, and adrain electrode layer each including a heat resistant conductivematerial above the oxide semiconductor layer; forming, over the gateinsulating layer, the oxide semiconductor layer, the connectionelectrode layer, the source electrode layer, and the drain electrodelayer, an oxide insulating film which is in contact with part of theoxide semiconductor layer; and performing dehydration or dehydrogenationon the oxide semiconductor layer after the oxide insulating film isformed.

With the above structure, at least one of the above problems can beresolved.

Another embodiment of the present invention is a method formanufacturing a semiconductor device including the steps of: forming agate electrode layer including a heat resistant conductive material overa substrate having an insulating surface; forming a gate insulatinglayer over the gate electrode layer; forming an oxide semiconductorlayer over the gate insulating layer; forming a connection electrodelayer, a source electrode layer, and a drain electrode layer eachincluding a heat resistant conductive material above the oxidesemiconductor layer; forming, over the gate insulating layer, the oxidesemiconductor layer, the connection electrode layer, the sourceelectrode layer, and the drain electrode layer, an oxide insulating filmwhich is in contact with part of the oxide semiconductor layer;performing dehydration or dehydrogenation on the oxide semiconductorlayer after the oxide insulating film is formed; removing part of theoxide insulating film and forming a first contact hole which reaches thesource electrode layer, and a third contact hole and a fourth contacthole which reach both end portions of the connection electrode layer;removing part of the oxide insulating film and part of the gateinsulating layer and forming a second contact hole which reaches thegate electrode layer; and forming, over the oxide insulating film, asource wiring which is connected to the source electrode layer throughthe first contact hole, a first gate wiring which is connected to thegate electrode layer through the second contact hole and to theconnection electrode layer through the third contact hole, and a secondgate wiring which is connected to the connection electrode layer throughthe fourth contact hole.

Another embodiment of the present invention is a method formanufacturing a semiconductor device including the steps of: forming agate electrode layer including a heat resistant conductive material overa substrate having an insulating surface; forming a gate insulatinglayer over the gate electrode layer; forming an oxide semiconductorlayer over the gate insulating layer; forming a connection electrodelayer, a source electrode layer, and a drain electrode layer eachincluding a heat resistant conductive material above the oxidesemiconductor layer; forming, over the gate insulating layer, the oxidesemiconductor layer, the connection electrode layer, the sourceelectrode layer, and the drain electrode layer, an oxide insulating filmwhich is in contact with part of the oxide semiconductor layer;performing dehydration or dehydrogenation on the oxide semiconductorlayer after the oxide insulating film is formed; removing part of theoxide insulating film and forming a first contact hole which reaches thesource electrode layer, and a third contact hole and a fourth contacthole which reach both end portions of the connection electrode layer;removing part of the oxide insulating film and part of the gateinsulating layer and forming a second contact hole which reaches thegate electrode layer; and forming, over the oxide insulating film, afirst source wiring which is connected to the source electrode layerthrough the first contact hole and to the connection electrode layerthrough the third contact hole, a second source wiring which isconnected to the connection electrode layer through the fourth contacthole, and a gate wiring which is connected to the gate electrode layerthrough the second contact hole.

In any of the structures of the manufacturing methods, the dehydrationor dehydrogenation is preferably heating under a nitrogen atmosphere, anoxygen atmosphere, or a rare gas atmosphere, or under reduced pressure,and the oxide semiconductor layer is more preferably heated at atemperature of higher than or equal to 350° C. and lower than a strainpoint of the substrate. Slow cooling is preferably performed after theheating.

As the heat resistant conductive material, an element selected fromtitanium, tantalum, tungsten, molybdenum, chromium, neodymium, orscandium; an alloy including any of these elements as a component; or anitride including any of these elements as a component is preferablyused in a single layer or a stacked layer. The source wiring and thegate wiring are preferably formed using a low resistance conductivematerial which has lower resistivity than the source electrode layer andthe drain electrode layer. Aluminum or copper is preferably used as thelow resistance conductive material.

Another embodiment of the present invention is a semiconductor deviceincluding a gate electrode layer formed using a first mask over asubstrate having an insulating surface; a gate insulating layer over thegate electrode layer; an oxide semiconductor layer formed using a secondmask over the gate insulating layer; a connection electrode layer, asource electrode layer, and a drain electrode layer which are formedusing a third mask, wherein the source electrode layer and the drainelectrode layer are above the oxide semiconductor layer; an oxideinsulating film which covers the gate insulating layer, the oxidesemiconductor layer, the source electrode layer, and the drain electrodelayer, wherein the oxide insulating film is in contact with part of theoxide semiconductor layer; and a gate wiring, a first source wiring, anda second source wiring which are formed using a fourth mask over theoxide insulating film. The first source wiring is electrically connectedto the source electrode layer, the gate wiring is electrically connectedto the gate electrode layer, the first source wiring and the secondsource wiring are electrically connected to the connection electrodelayer, and the connection electrode layer overlaps the gate wiring withthe oxide insulating film interposed therebetween. Here the first tofourth masks refer to photomasks.

Another embodiment of the present invention is a semiconductor deviceincluding: a gate electrode layer formed using a first mask over asubstrate having an insulating surface; a gate insulating layer over thegate electrode layer; an oxide semiconductor layer formed using a secondmask over the gate insulating layer; a connection electrode layer, asource electrode layer, and a drain electrode layer which are formedusing a third mask, wherein the source electrode layer and the drainelectrode layer are above the oxide semiconductor layer; an oxideinsulating film which covers the gate insulating layer, the oxidesemiconductor layer, the source electrode layer, and the drain electrodelayer, wherein the oxide insulating film is in contact with part of theoxide semiconductor layer; and a gate wiring, a first source wiring, anda second source wiring which are formed using a fourth mask over theoxide insulating film. The first source wiring is electrically connectedto the source electrode layer, the gate wiring is electrically connectedto the gate electrode layer, the first source wiring and the secondsource wiring are electrically connected to the connection electrodelayer; and the connection electrode layer overlaps the gate wiring withthe oxide insulating film interposed therebetween. Here the first tofourth masks refer to photomasks.

In any of the structures of the semiconductor devices, a single layer ora stacked layer of an element selected from titanium, tantalum,tungsten, molybdenum, chromium, neodymium, or scandium; an alloyincluding any of these elements as a component; or a nitride includingany of these elements as a component is preferably used for the gateelectrode layer, the connection electrode layer, the source electrodelayer, and the drain electrode layer. The source wiring and the gatewiring are preferably formed using a low resistance conductive materialwhich has lower resistivity than the source electrode layer and thedrain electrode layer, and aluminum or copper is more preferably used.

An oxide semiconductor used in this specification is formed into a thinfilm represented by InMO₃(ZnO)_(m) (m>0), and a thin film transistor ismanufactured using this thin film as an oxide semiconductor layer.However, m is not always an integer. Note that M represents one or moremetal elements selected from Ga, Fe, Ni, Mn, or Co. As an example, M maybe Ga or may include the above metal element in addition to Ga, forexample, M may be Ga and Ni or Ga and Fe. Moreover, in the above oxidesemiconductor, in some cases, a transition metal element such as Fe orNi or an oxide of the transition metal is contained as an impurityelement in addition to a metal element contained as M In thisspecification, among the oxide semiconductor layers whose compositionformulae are represented by InMO₃(ZnO)_(m) (m>0), an oxide semiconductorwhose composition formula includes at least Ga as M is referred to as anIn—Ga—Zn—O-based oxide semiconductor, and a thin film of theIn—Ga—Zn—O-based oxide semiconductor is referred to as anIn—Ga—Zn—O-based non-single-crystal film.

As the oxide semiconductor which is applied to the oxide semiconductorlayer, any of the following oxide semiconductors can be applied inaddition to the above: an In—Sn—Zn—O-based oxide semiconductor; anIn—Al—Zn—O-based oxide semiconductor; a Sn—Ga—Zn—O-based oxidesemiconductor; an Al—Ga—Zn—O-based oxide semiconductor; aSn—Al—Zn—O-based oxide semiconductor; an In—Zn—O-based oxidesemiconductor; a Sn—Zn—O-based oxide semiconductor; an Al—Zn—O-basedoxide semiconductor; an In—O-based oxide semiconductor; a Sn—O-basedoxide semiconductor; and a Zn—O-based oxide semiconductor. Silicon oxidemay be included in the oxide semiconductor layer. Further, silicon oxide(SiO_(x) (x>0)), which hinders crystallization, contained in the oxidesemiconductor layer can suppress crystallization of the oxidesemiconductor layer in the case where heat treatment is performed afterthe formation of the oxide semiconductor layer in the manufacturingprocess. Note that the oxide semiconductor layer is preferably anamorphous state and may be partly crystallized.

The change of the oxide semiconductor layer in an amorphous state to amicrocrystalline state or a polycrystalline state in some cases isdetermined by conditions of heat treatment or a material used to formthe oxide semiconductor layer.

Since a thin film transistor is easily broken due to static electricityor the like, a protective circuit for protecting a driver circuit ispreferably provided over the same substrate as a gate wiring or a sourcewiring. The protective circuit is preferably formed with a non-linearelement including an oxide semiconductor.

The gate insulating layer and the oxide semiconductor film may besuccessively subjected to treatment (also referred to as successivetreatment, an in-situ process, or successive film formation) withoutexposure to air. Successive treatment without exposure to air makes itpossible to obtain an interface between the gate insulating layer andthe oxide semiconductor film, which is not contaminated by atmosphericcomponents or impurities floating in air, such as water, hydrocarbon, orthe like. Therefore, variation in characteristics of the thin filmtransistor can be reduced.

Note that the term “successive treatment” in this specification meansthat during the process from a first treatment step by a PCVD method ora sputtering method to a second treatment step by a PCVD method or asputtering method, an atmosphere in which a substrate to be processed isdisposed is kept controlled to be vacuum or an inert gas atmosphere (anitrogen atmosphere or a rare gas atmosphere) without exposure to acontaminant atmosphere such as air. By the successive treatment,treatment such as film formation can be performed while preventingmoisture or the like from being attached again to the substrate to beprocessed which is cleaned.

Performing the process from the first treatment step to the secondtreatment step in the same chamber is within the scope of the successivetreatment in this specification.

In addition, the following is also within the scope of the successivetreatment in this specification: in the case of performing the processfrom the first treatment step to the second treatment step in differentchambers, the substrate is transferred after the first treatment step toanother chamber without exposure to air and subjected to the secondtreatment.

Note that the case where there is a substrate transfer step, analignment step, a slow cooling step, a step of heating or cooling asubstrate so that the temperature of the substrate is suitable to thesecond treatment step, or the like between the first treatment step andthe second treatment step is also in the range of the successivetreatment in this specification.

A step in which liquid is used, such as a cleaning step, wet etching, orformation of a resist may be provided between the first treatment stepand the second treatment step. This case is not within the scope of thesuccessive treatment in this specification.

A thin film transistor having stable electric characteristics can beprovided. Further, a semiconductor device including a highly reliablethin film transistor having favorable electric characteristics can beprovided.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1E are cross-sectional views illustrating a manufacturingprocess according to an embodiment of the present invention.

FIGS. 2A to 2D are plan views illustrating a manufacturing processaccording to an embodiment of the present invention.

FIGS. 3A to 3D are views illustrating semiconductor devices according toan embodiment of the present invention.

FIGS. 4A to 4E are cross-sectional views illustrating a manufacturingprocess according to an embodiment of the present invention.

FIGS. 5A to 5D are plan views illustrating a manufacturing processaccording to an embodiment of the present invention.

FIGS. 6A to 6D are views illustrating a semiconductor device accordingto an embodiment of the present invention.

FIGS. 7A to 7D are cross-sectional views illustrating a method formanufacturing a semiconductor device according to an embodiment of thepresent invention.

FIGS. 8A to 8C are cross-sectional views illustrating the method formanufacturing a semiconductor device according to an embodiment of thepresent invention.

FIGS. 9A and 9B are cross-sectional views illustrating the method formanufacturing a semiconductor device according to an embodiment of thepresent invention.

FIG. 10 is a plan view illustrating a method for manufacturing asemiconductor device according to an embodiment of the presentinvention.

FIG. 11 is a plan view illustrating a method for manufacturing asemiconductor device according to an embodiment of the presentinvention.

FIG. 12 is a plan view illustrating a method for manufacturing asemiconductor device according to an embodiment of the presentinvention.

FIG. 13 is a plan view illustrating a method for manufacturing asemiconductor device according to an embodiment of the presentinvention.

FIGS. 14A to 14D are views illustrating semiconductor devices accordingto an embodiment of the present invention.

FIG. 15 is a cross-sectional view illustrating an electric furnace.

FIG. 16 is a cross-sectional view illustrating an electric furnace.

FIG. 17 is a cross-sectional view illustrating a semiconductor deviceaccording to an embodiment of the present invention.

FIG. 18 is a cross-sectional view illustrating a semiconductor deviceaccording to an embodiment of the present invention.

FIGS. 19A to 19C are views illustrating a semiconductor device accordingto an embodiment of the present invention.

FIGS. 20A and 20B are cross-sectional views illustrating semiconductordevices according to an embodiment of the present invention.

FIG. 21 is a cross-sectional view illustrating a semiconductor deviceaccording to an embodiment of the present invention.

FIGS. 22A and 22B are block diagrams of display devices.

FIGS. 23A and 23B are a view illustrating a structure of a signal linedriver circuit and a timing chart thereof, respectively.

FIGS. 24A to 24C are circuit diagrams illustrating a structure of ashift register.

FIGS. 25A and 25B are a view illustrating an equivalent circuit of ashift register and a timing chart thereof showing operations of theshift register, respectively.

FIGS. 26A to 26C are views illustrating a semiconductor device.

FIG. 27 is a view illustrating a semiconductor device.

FIG. 28 is a view illustrating a semiconductor device.

FIG. 29 is a view illustrating a equivalent circuit of a pixel includedin a semiconductor device.

FIGS. 30A to 30C are views illustrating semiconductor devices.

FIGS. 31A and 31B are views illustrating a semiconductor device.

FIG. 32 is an external view of an example of an e-book reader.

FIG. 33A is an external view of an example of a television device, andFIG. 33B is an external view of an example of a digital photo frame.

FIGS. 34A and 34B are external views of examples of an amusementmachine.

FIG. 35A is an external view of an example of a portable computer, andFIG. 35B is an external view of an example of a cellular phone.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. However, the presentinvention is not limited to the description below, and it is easilyunderstood by those skilled in the art that modes and details disclosedherein can be modified in various ways without departing from the spiritand the scope of the present invention. Therefore, the present inventionis not construed as being limited to description of the embodiments.

Embodiment 1

FIG. 3A is a plan view of a thin film transistor 461 included in asemiconductor device, and FIG. 3B is a cross-sectional view taken alongline C1-C2 of FIG. 3A. The thin film transistor 461 is an invertedstaggered thin film transistor. A gate electrode layer 401 is providedover a substrate 400 having an insulating surface. A gate insulatinglayer 402 is provided over the gate electrode layer 401. An oxidesemiconductor layer 403 is provided over the gate insulating layer 402.A source electrode layer 405 a and a drain electrode layer 405 b areprovided over the oxide semiconductor layer 403. In addition, an oxideinsulating film 407 which covers the gate insulating layer 402, theoxide semiconductor layer 403, the source electrode layer 405 a and thedrain electrode layer 405 b and which is in contact with part of theoxide semiconductor layer 403 is provided.

The oxide insulating film 407 is provided with a first contact hole 421which reaches the source electrode layer 405 a, a second contact hole422 which reaches the gate electrode layer 401, and a third contact hole423 and a fourth contact hole 424 which reach both end portions of aconnection electrode layer 420. Here, in this embodiment, since a sourcewiring and a gate wiring are formed from the same layer, a first gatewiring 426 and a second gate wiring 427 are formed so as to sandwich asource wiring 425 therebetween. The first gate wiring 426 and the secondgate wiring 427 are electrically connected to each other through theconnection electrode layer 420 which is formed so as to overlap thesource wiring 425. Here, the source wiring 425 is electrically connectedto the source electrode layer 405 a through the first contact hole 421.The first gate wiring 426 is electrically connected to the gateelectrode layer 401 through the second contact hole 422. The first gatewiring 426 and the second gate wiring 427 are electrically connected tothe connection electrode layer 420 through the third contact hole 423and the fourth contact hole 424. The source wiring 425, the first gatewiring 426, and the second gate wiring 427 extend beyond the perimeterof the oxide semiconductor layer 403.

After the oxide insulating film 407 serving as a protective film isformed in contact with the oxide semiconductor layer 403, heat treatmentfor reducing impurities such as moisture (heat treatment for dehydrationor dehydrogenation) is performed on the oxide semiconductor layer 403.

Impurities such as moisture, which exist not only in the oxidesemiconductor layer 403 but also in the gate insulating layer 402, inthe source electrode layer 405 a, in the drain electrode layer 405 b,and at interfaces between the oxide semiconductor layer 403 and upperand lower films which are in contact with the oxide semiconductor layer403, specifically, at an interface between the gate insulating layer 402and the oxide semiconductor layer 403 or at an interface between theoxide insulating film 407 and the oxide semiconductor layer 403, arereduced. When the moisture or the like content in the oxidesemiconductor layer 403 is reduced with the heat treatment, electriccharacteristics of the thin film transistor can be improved.

With this heat treatment, plasma damage which is caused to the oxidesemiconductor layer 403 is repaired when the oxide insulating film 407is formed.

Each of the gate electrode layer 401, the connection electrode layer420, the source electrode layer 405 a, and the drain electrode layer 405b preferably includes a heat resistant conductive material. As the heatresistant conductive material, an element selected from titanium,tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; analloy including any of these elements as a component; or a nitrideincluding any of these elements as a component can be used. The gateelectrode layer 401, the connection electrode layer 420, the sourceelectrode layer 405 a, and the drain electrode layer 405 b may have astacked structure of an element selected from titanium, tantalum,tungsten, molybdenum, chromium, neodymium, or scandium; an alloyincluding any of these elements as a component; or a nitride includingany of these elements as a component. For example, a combination oftungsten nitride for a first layer and tungsten for a second layer, acombination of molybdenum nitride for the first layer and tungsten forthe second layer, or a combination of titanium nitride for the firstlayer and titanium for the second layer may be employed.

For the heat resistant conductive material used for the connectionelectrode layer 420, the source electrode layer 405 a, and the drainelectrode layer 405 b, a transparent conductive oxide containing any ofindium, tin, or zinc may be used. For example, indium oxide (In₂O₃) oran indium oxide-tin oxide (In₂O₃—SnO₂, abbreviated to ITO) alloy ispreferably used. Alternatively, a transparent conductive oxide to whichan insulating oxide such as silicon oxide is added may be used.

By inclusion of the insulating oxide such as silicon oxide in thetransparent conductive oxide, crystallization of the transparentconductive oxide can be suppressed and the transparent conductive oxidecan have an amorphous structure. Crystallization of the transparentconductive oxide is suppressed and an amorphous structure is formed, sothat crystallization of the transparent conductive oxide or generationof microcrystalline grains can be prevented even when heat treatment isperformed.

When such a heat resistant conductive material is included in the gateelectrode layer 401, the connection electrode layer 420, the sourceelectrode layer 405 a, and the drain electrode layer 405 b, the gateelectrode layer 401, the connection electrode layer 420, the sourceelectrode layer 405 a, and the drain electrode layer 405 b can endurethe heat treatment which is performed after the oxide insulating film407 is formed.

The source wiring 425, the first gate wiring 426, and the second gatewiring 427 are preferably formed using a low resistance conductivematerial which has lower resistivity than the source electrode layer 405a and the drain electrode layer 405 b, and aluminum or copper isparticularly preferable. With the use of the low resistance conductivematerial for the source wiring 425, the first gate wiring 426, and thesecond gate wiring 427, wiring resistance or the like can be reduced.

The low resistance conductive material such as aluminum or copper haslow heat resistance. However, the heat treatment is performed afterforming the oxide insulating film, and then the source wiring 425, thefirst gate wiring 426, and the second gate wiring 427 are provided,whereby the above low resistance conductive material can be used as thesource wiring 425, the first gate wiring 426, and the second gate wiring427.

As the oxide semiconductor layer 403 including a channel formationregion, an oxide material having semiconductor characteristics may beused, and typically, In—Ga—Zn—O-based non-single-crystal is used.

As illustrated in FIG. 3C, a first source wiring 428 and a second sourcewiring 429 may be formed so as to sandwich a gate wiring 430therebetween and may be electrically connected to each other through theconnection electrode layer 420 which is formed so as to overlap the gatewiring 430. Here, the first source wiring 428 is electrically connectedto the source electrode layer 405 a through the first contact hole 421.The gate wiring 430 is electrically connected to the gate electrodelayer 401 through the second contact hole 422. The first source wiring428 and the second source wiring 429 are electrically connected to theconnection electrode layer 420 through the third contact hole 423 andthe fourth contact hole 424 which reach both end portions of theconnection electrode layer 420. The other portions are similar to thoseof the thin film transistor illustrated in FIGS. 3A and 3B.

As illustrated in FIG. 3D, the source electrode layer 405 a may beformed so as to overlap the gate wiring 430, and the first source wiring428 and the second source wiring 429 may be electrically connected toeach other through the source electrode layer 405 a. Here, the firstsource wiring 428 is electrically connected to the source electrodelayer 405 a through the first contact hole 421. The second source wiring429 is electrically connected to the source electrode layer 405 athrough a third contact hole 490 provided over the source electrodelayer 405 a. The other portions are similar to those of the thin filmtransistor illustrated in FIG. 3C.

FIGS. 1A to 1E are cross-sectional views of a manufacturing process ofthe thin film transistor 461 illustrated in FIGS. 3A and 3B, and FIGS.2A to 2D are plan views of the manufacturing process.

First, over the substrate 400 having an insulating surface, the gateelectrode layer 401 is provided using a photolithography process withthe use of a photomask.

Although there is no particular limitation on a glass substrate whichcan be used, it is necessary that the glass substrate have at leastenough heat resistance to heat treatment to be performed later. As thelight-transmitting substrate 400, it is possible to use a glasssubstrate made of barium borosilicate glass, aluminoborosilicate glass,or the like.

As the substrate 400, a substrate whose strain point is higher than orequal to 730° C. may be used when the temperature of later heattreatment is high. Further, as a material of the substrate 400, forexample, a glass material such as aluminosilicate glass,aluminoborosilicate glass, or barium borosilicate glass is used. Notethat by containing a larger amount of barium oxide (BaO) than boricacid, a glass substrate is heat-resistant and of more practical use.Therefore, a glass substrate containing a larger amount of BaO than B₂O₃is preferably used.

Note that a substrate formed of an insulator such as a ceramicsubstrate, a quartz glass substrate, a quartz substrate, or a sapphiresubstrate may be used instead of the glass substrate 400. Alternatively,crystallized glass or the like may be used.

An insulating film serving as a base film may be provided between thesubstrate 400 and the gate electrode layer 401. The base film has afunction of preventing diffusion of an impurity element from thesubstrate 400, and can be formed to have a single-layer or stackedstructure using one or more of a silicon nitride film, a silicon oxidefilm, a silicon nitride oxide film, and a silicon oxynitride film.

Since heat treatment is performed in a later step, a material of thegate electrode layer 401 preferably includes a heat resistant conductivematerial. As the heat resistant conductive material, an element selectedfrom titanium, tantalum, tungsten, molybdenum, chromium, neodymium, orscandium; an alloy including any of these elements as a component; or anitride including any of these elements as a component can be used. Thegate electrode layer 401 may have a single-layer or stacked structure ofan element selected from titanium, tantalum, tungsten, molybdenum,chromium, neodymium, or scandium; an alloy including any of theseelements as a component; or a nitride including any of these elements asa component. For example, a combination of tungsten nitride for a firstlayer and tungsten for a second layer, a combination of molybdenumnitride for the first layer and tungsten for the second layer, or acombination of titanium nitride for the first layer and titanium for thesecond layer may be employed. However, a material of the gate electrodelayer 401 preferably has heat resistance that can withstand at leastlater heat treatment.

At this time, the connection electrode layer 420 which is formed at thesame time as the formation of the source electrode layer 405 a and thedrain electrode layer 405 b in a later step may be formed at the sametime as the formation of the gate electrode layer 401. In that case, theconnection electrode layer 420 is not necessarily formed when the sourceelectrode layer 405 a and the drain electrode layer 405 b are formed.

Next, the gate insulating layer 402 is formed over the gate electrodelayer 401.

The gate insulating layer can be formed as a single layer or a stackedlayer using any of a silicon oxide layer, a silicon nitride layer, asilicon oxynitride layer, and a silicon nitride oxide layer by a plasmaenhanced CVD method, a sputtering method, or the like. For example, asilicon oxynitride layer may be formed using a deposition gas containingSiH₄, oxygen, and nitrogen by a plasma enhanced CVD method.

Next, an oxide semiconductor film is formed over the gate insulatinglayer 402.

Note that before the oxide semiconductor film is formed by a sputteringmethod, powdery substances (also referred to as particles or dust) whichare generated at the time of the film formation and attached on asurface of the gate insulating layer 402 are preferably removed byreverse sputtering in which an argon gas is introduced and plasma isgenerated. The reverse sputtering refers to a method in which an RFpower supply is used for application of voltage to a substrate side inan argon atmosphere and plasma is generated around the substrate tomodify a surface. Note that instead of an argon atmosphere, a nitrogenatmosphere, a helium atmosphere, or the like may be used.

The oxide semiconductor film is formed by a sputtering method with theuse of an In—Ga—Zn—O-based oxide semiconductor target. Alternatively,the oxide semiconductor film can be formed by a sputtering method undera rare gas (typically, argon) atmosphere, an oxygen atmosphere, or anatmosphere containing a rare gas (typically, argon) and oxygen.

The gate insulating layer 402 and the oxide semiconductor film may beformed successively without exposure to air. Successive film formationwithout exposure to air makes it possible to obtain each interfacebetween stacked layers, which is not contaminated by atmosphericcomponents or impurity elements floating in air, such as water,hydrocarbon, or the like. Therefore, variation in characteristics of thethin film transistor can be reduced.

The oxide semiconductor film is processed into an island-shaped oxidesemiconductor layer using a photolithography process with the use of aphotomask.

Next, a first conductive film is formed over the gate insulating layer402 and the oxide semiconductor layer.

The material used for the first conductive film preferably includes aheat resistant conductive material in order to perform heat treatment ina later process. As the heat resistant conductive material, an elementselected from titanium, tantalum, tungsten, molybdenum, chromium,neodymium, or scandium; an alloy including any of these elements as acomponent; or a nitride including any of these elements as a componentcan be used. The first conductive film may have a single-layer orstacked structure of an element selected from titanium, tantalum,tungsten, molybdenum, chromium, neodymium, or scandium; an alloyincluding any of these elements as a component; or a nitride includingany of these elements as a component. For example, a combination oftungsten nitride for a first layer and tungsten for a second layer, acombination of molybdenum nitride for the first layer and tungsten forthe second layer, or a combination of titanium nitride for the firstlayer and titanium for the second layer may be used. However, a materialof the first conductive film preferably has heat resistance that canwithstand at least later heat treatment.

For the heat resistant conductive material used for the first conductivefilm, a transparent conductive oxide containing any of indium, tin, orzinc may be used. For example, indium oxide (In₂O₃) or an indiumoxide-tin oxide (In₂O₃—SnO₂, abbreviated to ITO) alloy is preferablyused. Alternatively, a transparent conductive oxide to which aninsulating oxide such as silicon oxide is added may be used.

By inclusion of the insulating oxide such as silicon oxide in thetransparent conductive oxide, crystallization of the transparentconductive oxide can be suppressed and the transparent conductive oxidecan have an amorphous structure. Crystallization of the transparentconductive oxide is suppressed and an amorphous structure is provided,so that crystallization of the transparent conductive oxide orgeneration of microcrystalline grains can be prevented even when heattreatment is performed.

The oxide semiconductor layer and the first conductive film areprocessed into an oxide semiconductor layer 432, the source electrodelayer 405 a, the drain electrode layer 405 b, and the connectionelectrode layer 420 using a photolithography with the use of a photomask(see FIG. 1A and FIG. 2A). Note that only part of the oxidesemiconductor layer is etched to be the oxide semiconductor layer 432having a groove (depression).

The connection electrode layer 420 is not necessarily formed when theconnection electrode layer 420 is formed at the same time as theformation of the gate electrode layer 401. Also in the case of havingthe structure illustrated in FIG. 3D, the connection electrode layer 420is not necessarily formed.

The oxide insulating film 407 which covers the gate insulating layer402, the oxide semiconductor layer 432, the source electrode layer 405a, and the drain electrode layer 405 b and which is in contact with partof the oxide semiconductor layer 432 is formed (see FIG. 1B). The oxideinsulating film 407 can be formed to a thickness of at least 1 nm ormore using a method by which impurities such as water and hydrogen areprevented from being mixed to the oxide insulating film 407, such as aCVD method or a sputtering method, as appropriate. Here, the oxideinsulating film 407 is formed using a sputtering method. The oxideinsulating film 407 which is in contact with part of the oxidesemiconductor layer 432 does not include impurities such as moisture,hydrogen ions, and OH⁻ and is formed using an inorganic insulating filmwhich prevents entry of these from the outside. Specifically, a siliconoxide film, a silicon nitride oxide film, an aluminum oxide film, or analuminum oxynitride film is used. Further, a silicon nitride film or analuminum nitride film may be stacked so as to be formed over and incontact with the oxide insulating film 407. The silicon nitride filmdoes not include impurities such as moisture, hydrogen ions, and OW andprevents entry of these from the outside.

When slow cooling is performed under an oxygen atmosphere after heattreatment to be performed later, a region including oxygen at highconcentration near a surface of the oxide semiconductor layer can beformed, and the oxide semiconductor layer can have sufficient highresistance, a silicon nitride film may be formed instead of the oxideinsulating film 407. For example, slow cooling may be performed so thatthe substrate temperature is lowered by at least approximately 50° C. to100° C. from the highest heating temperature.

In this embodiment, a silicon oxide film having a thickness of 300 nm isformed as the oxide insulating film 407. The substrate temperature atthe time of film formation may be higher than or equal to a roomtemperature and lower than or equal to 300° C., and the temperature isset at 100° C. in this embodiment. The silicon oxide film can be formedby a sputtering method under a rare gas (typically, argon) atmosphere,an oxygen atmosphere, or an atmosphere containing a rare gas (typically,argon) and oxygen. In addition, a silicon oxide target or a silicontarget can be used as a target. For example, the silicon oxide film canbe formed using a silicon target by a sputtering method under anatmosphere containing oxygen and nitrogen.

Next, heat treatment is performed on the source electrode layer 405 a,the drain electrode layer 405 b, the gate insulating layer 402, theoxide insulating film 407, and the oxide semiconductor layer 432 underan oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium,neon, argon, or the like), or under reduced pressure, whereby the oxidesemiconductor layer 403 is formed (see FIG. 1C and FIG. 2B). The heattreatment is performed at a temperature of higher than or equal to 200°C. and lower than or equal to 700° C., preferably, higher than or equalto 350° C. and lower than the strain point of the substrate 400. Whenthe heat treatment is performed on the source electrode layer 405 a, thedrain electrode layer 405 b, the gate insulating layer 402, the oxideinsulating film 407, and the oxide semiconductor layer 403 under theabove atmosphere, impurities such as hydrogen and water included in thesource electrode layer 405 a, in the drain electrode layer 405 b, in thegate insulating layer 402, in the oxide insulating film 407, and in theoxide semiconductor layer 403, and at interfaces between the oxidesemiconductor layer 403 and upper and lower films which are in contactwith the oxide semiconductor layer 403 can be removed. In accordancewith conditions of the heat treatment or a material of the oxidesemiconductor layer, the oxide semiconductor layer is crystallized andchanged to a microcrystalline film or a polycrystalline film in somecases.

When the oxide insulating film 407 serving as a protective film isformed in contact with the oxide semiconductor layer 432, there is apossibility that the oxide semiconductor layer 432 might receive plasmadamage. However, with the heat treatment, plasma damage which is causedto the oxide semiconductor layer 432 can be repaired.

With this heat treatment, oxygen in the oxide insulating film 407 issupplied to the oxide semiconductor layer 403 using solid-phasediffusion. Accordingly, since the resistance of the oxide semiconductorlayer 403 increases, a highly reliable thin film transistor withfavorable electric characteristics can be manufactured.

The heat treatment can reduce variation in electric characteristics ofthe thin film transistor.

Note that in heat treatment, it is preferable that water, hydrogen, andthe like be not contained in nitrogen or a rare gas such as helium,neon, or argon. Alternatively, it is preferable that nitrogen or a raregas such as helium, neon, or argon introduced into an apparatus for heattreatment have purity of 6N (99.9999%) or more, preferably, 7N(99.99999%) or more, that is, an impurity concentration is set to 1 ppmor lower, preferably, 0.1 ppm or lower. After the heat treatment, slowcooling is preferably performed under an oxygen atmosphere. For example,slow cooling may be performed so that the substrate temperature islowered by at least approximately 50° C. to 100° C. from the highestheating temperature.

As the heat treatment, an instantaneous heating method can be employed,such as a heating method using an electric furnace, a gas rapid thermalannealing (GRTA) method using a heated gas, or a lamp rapid thermalanneal (LRTA) method using lamp light.

Here, as an embodiment of heat treatment of the source electrode layer405 a, the drain electrode layer 405 b, the gate insulating layer 402,the oxide insulating film 407, and the oxide semiconductor layer 432, aheating method using an electric furnace 601 will be described withreference to FIG. 15.

FIG. 15 is a schematic view of the electric furnace 601. Heaters 603 areprovided outside a chamber 602, which heats the chamber 602. Inside thechamber 602, a susceptor 605 in which a substrate 604 is mounted isprovided. The substrate 604 is transferred into/from the chamber 602. Inaddition, the chamber 602 is provided with a gas supply means 606 and anevacuation means 607. With the gas supply means 606, a gas is introducedinto the chamber 602. The evacuation means 607 exhausts the inside ofthe chamber 602 or reduces the pressure in the chamber 602. Note thatthe temperature rise characteristics of the electric furnace 601 arepreferably set to from 0.1° C./min to 20° C./min, inclusive. Thetemperature drop characteristics of the electric furnace 601 arepreferably set to from 0.1° C./min to 15° C./min, inclusive.

The gas supply means 606 includes a gas supply source 611 a, a gassupply source 611 b, a pressure regulation valve 612 a, a pressureregulation valve 612 b, a refiner 613 a, a refiner 613 b, a mass flowcontroller 614 a, a mass flow controller 614 b, a stop valve 615 a, anda stop valve 615 b. In this embodiment, the refiner 613 a and therefiner 613 b are preferably provided between the gas supply source 611a and the chamber 602 and between the gas supply source 611 b and thechamber 602, respectively. The refiner 613 a and the refiner 613 b canremove impurities such as water and hydrogen in a gas which isintroduced into the chamber 602 from the gas supply source 611 a and thegas supply source 611 b; thus, entry into the chamber 602 of water,hydrogen, and the like, can be suppressed by provision of the refiner613 a and the refiner 613 b.

In this embodiment, nitrogen or a rare gas is introduced into thechamber 602 from the gas supply source 611 a or the gas supply source611 b, respectively, so that the inside of the chamber is in an oxygenatmosphere, a nitrogen atmosphere, or a rare gas atmosphere. In thechamber 602 which is heated at a temperature of higher than or equal to200° C. and lower than or equal to 700° C., preferably, higher than orequal to 350° C. and lower than the strain point of the substrate 400,the oxide semiconductor layer 432 formed over the substrate 400 isheated, whereby the oxide semiconductor layer 432 can be subjected todehydration or dehydrogenation.

Alternatively, the chamber 602 in which the pressure is reduced by theevacuation means is heated at a temperature of higher than or equal to200° C. and lower than or equal to 700° C., preferably, higher than orequal to 350° C. and lower than the strain point of the substrate 400.In such a chamber 602, the oxide semiconductor layer 432 formed over thesubstrate 400 is heated, whereby the oxide semiconductor layer 432 canbe subjected to dehydration or dehydrogenation.

Next, introduction of nitrogen or a rare gas from the gas supply source611 a into the chamber 602 is stopped, and the heaters are turned off.Then, oxygen is introduced from the gas supply source 611 b into thechamber 602, and the chamber 602 of a heating apparatus is graduallycooled. That is, the chamber 602 has an oxygen atmosphere, and thesubstrate 604 is gradually cooled. Here, impurities such as water andhydrogen are preferably not included in oxygen which is introduced fromthe gas supply source 611 b into the chamber 602. Alternatively, thepurity of oxygen introduced from the gas supply source 611 b into thechamber 602 is preferably 6N (99.9999%) or more, more preferably, 7N(99.99999%) or more, that is, an impurity concentration in oxygen is setto 1 ppm or lower, preferably, 0.1 ppm or lower.

As a result, reliability of the thin film transistor to be formed latercan be improved.

Note that when heat treatment is performed under reduced pressure,oxygen may be introduced into the chamber 602 after the heat treatment,pressure may be returned to atmospheric pressure, and then cooling maybe performed.

Alternatively, oxygen is introduced from the gas supply source 611 binto the chamber 602, and at the same time, one of or both nitrogen anda rare gas such as helium, neon, or argon may be introduced into thechamber 602.

After the substrate 604 in the chamber 602 of the heating apparatus iscooled to 300° C., the substrate 604 may be transferred into anatmosphere at room temperature. As a result, the cooling time of thesubstrate 604 can be shortened.

When the heating apparatus has a multi-chamber structure, heat treatmentand cooling treatment can be performed in chambers different from eachother. Typically, an oxide semiconductor layer over a substrate isheated in a first chamber that is filled with oxygen, nitrogen, or arare gas and heated at a temperature of higher than or equal to 200° C.and lower than or equal to 700° C., preferably, higher than or equal to350° C. and lower than the strain point of the substrate 400. Next, thesubstrate which has been subjected to the heat treatment is transferred,through the transfer chamber in which nitrogen or a rare gas isintroduced, into a second chamber that is filled with oxygen and heatedat a temperature of lower than or equal to 100° C., preferably at roomtemperature, and then cooling treatment is performed therein. Throughthis process, throughput can be increased.

Although the oxide semiconductor layer 432 which has been subjected toheat treatment under an inert gas atmosphere or reduced pressure ispreferably an amorphous state, part of the oxide semiconductor layer 432may be crystallized.

As described above, when heat treatment is performed after the oxideinsulating film serving as a protective film is formed in contact withthe oxide semiconductor layer, impurities (H₂O, H, OH, or the like)included in the source electrode layer, the drain electrode layer, thegate insulating layer, the oxide insulating film, and the oxidesemiconductor layer can be reduced. With the heat treatment, plasmadamage which is caused to the oxide semiconductor layer when the oxideinsulating film serving as a protective film is formed in contact withthe oxide semiconductor layer can be repaired. The heat treatment canreduce variation in electric characteristics of the thin filmtransistor. As described above, electric characteristics and reliabilityof the thin film transistor 461 can be improved.

Next, the first contact hole 421, the second contact hole 422, the thirdcontact hole 423, and the fourth contact hole 424 are formed in theoxide insulating film 407 (see FIG. 1D and FIG. 2C). First, when part ofthe oxide insulating film 407 is removed by etching, the first contacthole 421 which reaches the source electrode layer 405 a, part of thesecond contact hole 422 which reaches the gate electrode layer 401, andthe third contact hole 423 and the fourth contact hole 424 which reachboth end portions of the connection electrode layer 420 are formed.Further, part of the gate insulating layer 402 is removed by etching, sothat the second contact hole 422 which reaches the gate electrode layer401 is formed.

Next, a second conductive film is formed over the oxide insulating film407. Here, the second conductive film is connected to the sourceelectrode layer 405 a, the gate electrode layer 401, and the connectionelectrode layer 420 through the first contact hole 421, the secondcontact hole 422, the third contact hole 423, and the fourth contacthole 424.

The second conductive film is preferably formed using a low resistanceconductive material which has lower resistivity than the sourceelectrode layer 405 a and the drain electrode layer 405 b, and aluminumor copper is particularly preferable. With the use of the low resistanceconductive material for the second conductive film, wiring resistance orthe like can be reduced.

Although the low resistance conductive material such as aluminum orcopper has low heat resistivity, the second conductive film can beprovided after the heat treatment; therefore, the low resistanceconductive material such as aluminum or copper can be used.

Next, the second conductive film is processed using a photolithographyprocess with the use of a photomask, so that the source wiring 425, thefirst gate wiring 426, and the second gate wiring 427 are formed overthe oxide insulating film 407 (see FIG. 1E and FIG. 2D). The sourcewiring 425 is formed so as to overlap the connection electrode layer 420and so as to be connected to the source electrode layer 405 a throughthe first contact hole 421. The first gate wiring 426 and the secondgate wiring 427 are formed so as to sandwich the source wiring 425therebetween. Here, the first gate wiring 426 is formed so as to beconnected to the gate electrode layer 401 through the second contacthole 422 and so as to be connected to the connection electrode layer 420through the third contact hole 423. The second gate wiring 427 is formedso as to be connected to the connection electrode layer 420 through thefourth contact hole 424. Accordingly, the first gate wiring 426 and thesecond gate wiring 427 are electrically connected to each other throughthe connection electrode layer 420.

Through the above process, the thin film transistor 461 can be formed.The structures illustrated in FIGS. 3C and 3D can be manufactured in asimilar process.

As described above, when heat treatment is performed after the oxideinsulating film serving as a protective film is formed in contact withthe oxide semiconductor layer, impurities (H₂O, H, OH, or the like)included in the source electrode layer, the drain electrode layer, thegate insulating layer, and the oxide semiconductor layer can be reduced.With the heat treatment, plasma damage which is caused to the oxidesemiconductor layer when the oxide insulating film serving as aprotective film is formed in contact with the oxide semiconductor layercan be repaired. The heat treatment can reduce variation in electriccharacteristics of the thin film transistor. Therefore, reliability ofthe thin film transistor 461 can be improved.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 2

A semiconductor device and a method for manufacturing the semiconductordevice will be described with reference to FIGS. 4A to 4E, FIGS. 5A to5D, and FIGS. 6A to 6D. The same portion as Embodiment 1 or a portionhaving similar function to that described in Embodiment 1 can be formedin a manner similar to that described in Embodiment 1; therefore,repetitive description is omitted.

FIG. 6A is a plan view of a thin film transistor 460 included in asemiconductor device, and FIG. 6B is a cross-sectional view taken alongline D1-D2 of FIG. 6A. The thin film transistor 460 is an invertedstaggered thin film transistor. A gate electrode layer 451 is providedover a substrate 450 having an insulating surface. A gate insulatinglayer 452 is provided over the gate electrode layer 451. A sourceelectrode layer 455 a and a drain electrode layer 455 b are providedover the gate insulating layer 452. An oxide semiconductor layer 453 isprovided over the source electrode layer 455 a, the drain electrodelayer 455 b, and the gate insulating layer 452. An oxide insulating film457 which covers the gate insulating layer 452, the oxide semiconductorlayer 453, the source electrode layer 455 a, and the drain electrodelayer 455 b and which is in contact with the oxide semiconductor layer453 is provided. An In—Ga—Zn—O-based non-single-crystal film is used forthe oxide semiconductor layer 453.

The oxide insulating film 457 is provided with a first contact hole 471which reaches the source electrode layer 455 a, a second contact hole472 which reaches the gate electrode layer 451, and a third contact hole473 and a fourth contact hole 474 which reach both end portions of aconnection electrode layer 470. Here, in this embodiment, a sourcewiring and a drain wiring are formed from the same layer;

therefore, a first gate wiring 476 and a second gate wiring 477 areformed so as to sandwich a source wiring 475 therebetween. The firstgate wiring 476 and the second gate wiring 477 are electricallyconnected to each other through the connection electrode layer 470 whichis formed so as to overlap the source wiring 475. Here, the sourcewiring 475 is electrically connected to the source electrode layer 455 athrough the first contact hole 471. The first gate wiring 476 iselectrically connected to the gate electrode layer 451 through thesecond contact hole 472. The first gate wiring 476 and the second gatewiring 477 are electrically connected to the connection electrode layer470 through the third contact hole 473 and the fourth contact hole 474.The source wiring 475, the first gate wiring 476, and the second gatewiring 477 extend beyond the perimeter of the oxide semiconductor layer453.

After the oxide insulating film 457 serving as a protective film isformed in contact with the oxide semiconductor layer 453, heat treatmentfor reducing impurities such as moisture (heat treatment for dehydrationor dehydrogenation) is performed on the oxide semiconductor layer 453.

Impurities such as moisture which exist not only in the oxidesemiconductor layer 453 but also in the gate insulating layer 452, inthe source electrode layer 455 a, in the drain electrode layer 455 b, orat interfaces between the oxide semiconductor layer 453 and upper andlower films which are in contact with the oxide semiconductor layer 453,specifically, at an interface between the gate insulating layer 452 andthe oxide semiconductor layer 453 or at an interface between the oxideinsulating film 457 and the oxide semiconductor layer 453 are reduced.When the moisture content or the like in the oxide semiconductor layer453 is reduced with the heat treatment, electric characteristics of thethin film transistor can be improved.

With the heat treatment, plasma damage which is caused to the oxidesemiconductor layer 453 when the oxide insulating film 457 is formed isrepaired.

Each of the gate electrode layer 451, the connection electrode layer470, the source electrode layer 455 a, and the drain electrode layer 455b preferably includes a heat resistant conductive material. As the heatresistant conductive material, an element selected from titanium,tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; analloy including any of these elements as a component; or a nitrideincluding any of these elements as a component can be used. The gateelectrode layer 451, the connection electrode layer 470, the sourceelectrode layer 455 a, and the drain electrode layer 455 b may have astacked structure of an element selected from titanium, tantalum,tungsten, molybdenum, chromium, neodymium, or scandium; an alloyincluding any of these elements as a component; or a nitride includingany of these elements as a component. For example, a combination oftungsten nitride for a first layer and tungsten for a second layer, acombination of molybdenum nitride for the first layer and tungsten forthe second layer, or a combination of titanium nitride for the firstlayer and titanium for the second layer may be employed.

For the heat resistant conductive material used for the connectionelectrode layer 470, the source electrode layer 455 a, and the drainelectrode layer 455 b, a transparent conductive oxide containing any ofindium, tin, or zinc may be used. For example, indium oxide (In₂O₃) oran indium oxide-tin oxide (In₂O₃—SnO₂, abbreviated to ITO) alloy ispreferably used. Alternatively, a transparent conductive oxide to whichan insulating oxide such as silicon oxide is added may be used.

By inclusion of the insulating oxide such as silicon oxide in thetransparent conductive oxide, crystallization of the transparentconductive oxide can be suppressed and the transparent conductive oxidecan have an amorphous structure. Crystallization of the transparentconductive oxide is suppressed and the transparent conductive oxide hasan amorphous structure, so that crystallization of the transparentconductive oxide or generation of microcrystalline grains can beprevented even when heat treatment is performed.

Such a heat resistant conductive material is included in the gateelectrode layer 451, the connection electrode layer 470, the sourceelectrode layer 455 a, and the drain electrode layer 455 b, whereby thegate electrode layer 451, the connection electrode layer 470, the sourceelectrode layer 455 a, and the drain electrode layer 455 b can endureheat treatment which is performed after the oxide insulating film 457 isformed.

The source wiring 475, the first gate wiring 476, and the second gatewiring 477 are preferably formed using a low resistance conductivematerial which has lower resistivity than the source electrode layer 455a and the drain electrode layer 455 b, and aluminum or copper isparticularly preferable. With the use of the low resistance conductivematerial for the source wiring 475, the first gate wiring 476, and thesecond gate wiring 477, wiring resistance or the like can be reduced.

The low resistance conductive material such as aluminum or copper haslow heat resistance. However, when the source wiring 475, the first gatewiring 476, and the second gate wiring 477 are provided after performingheat treatment and forming the oxide insulating layer, and then theabove low resistance conductive material can be used as the sourcewiring 475, the first gate wiring 476, and the second gate wiring 477.

As the oxide semiconductor layer 453 including a channel formationregion, an oxide material having semiconductor characteristics may beused, and typically, In—Ga—Zn—O-based non-single-crystal is used.

As illustrated in FIG. 6C, a first source wiring 478 and a second sourcewiring 479 may be formed so as to sandwich a gate wiring 480therebetween and may be electrically connected to each other through theconnection electrode layer 470 which is formed so as to overlap the gatewiring 480. Here, the first source wiring 478 is electrically connectedto the source electrode layer 455 a through the first contact hole 471.The gate wiring 480 is electrically connected to the gate electrodelayer 451 through the second contact hole 472. The first source wiring478 and the second source wiring 479 are electrically connected to theconnection electrode layer 470 through the third contact hole 473 andthe fourth contact hole 474 which reach both end portions of theconnection electrode layer 470. The other portions are similar to thoseof the thin film transistor illustrated in FIGS. 6A and 6B.

As illustrated in FIG. 6D, the source electrode layer 455 a may beformed so as to overlap the gate wiring 480, and the first source wiring478 and the second source wiring 479 may be electrically connected toeach other through the source electrode layer 455 a. Here, the firstsource wiring 478 is electrically connected to the source electrodelayer 455 a through the first contact hole 471. The second source wiring479 is electrically connected to the source electrode layer 455 athrough a third contact hole 491 provided over the source electrodelayer 455 a. The other portions are similar to those of the thin filmtransistor illustrated in FIG. 6C.

FIGS. 4A to 4E are cross-sectional views of a manufacturing process ofthe thin film transistor 460 illustrated in FIGS. 6A and 6B, while FIGS.5A to 5D are plan views of the manufacturing process.

The gate electrode layer 451 is provided over the substrate 450 which isa substrate having an insulating surface. An insulating film serving asa base film may be provided between the substrate 450 and the gateelectrode layer 451. The gate electrode layer 451 can be formed using amaterial which is similar to that of the gate electrode layer 401described in Embodiment 1.

In a manner similar to that of Embodiment 1, the connection electrodelayer 470 which is formed at the same time as the formation of thesource electrode layer 455 a and the drain electrode layer 455 b in alater step may be formed at the same time as the formation of the gateelectrode layer 451. In that case, the connection electrode layer 470 isnot necessarily formed when the source electrode layer 455 a and thedrain electrode layer 455 b are formed.

The gate insulating layer 452 is formed over the gate electrode layer451. The gate insulating layer 452 can be formed in a manner similar tothat of the gate insulating layer 402 described in Embodiment 1.

A first conductive film is formed over the gate insulating layer 452 andpatterned into the island-shaped source electrode layer 455 a, theisland-shaped drain electrode layer 455 b, and the connection electrodelayer 470 by a photolithography process. The first conductive film canbe formed using a material which is similar to the material used for thefirst conductive film described in Embodiment 1. The source electrodelayer 455 a and the drain electrode layer 455 b can be formed in amanner similar to that of the source electrode layer 405 a and the drainelectrode layer 405 b described in Embodiment 1.

When the connection electrode layer 470 is formed at the same time asthe formation of the gate electrode layer 451, the connection electrodelayer 470 is not necessarily formed here. Also in the case of havingsuch a structure as illustrated in FIG. 6D, the connection electrodelayer 470 is not necessarily formed.

Then, an oxide semiconductor film is formed over the gate insulatinglayer 452, the source electrode layer 455 a, and the drain electrodelayer 455 b and patterned into an island-shaped oxide semiconductorlayer 482 by a photolithography process (see FIG. 4A and FIG. 5A).

The oxide semiconductor layer 482 serves as a channel formation regionand is thus formed in a manner similar to the oxide semiconductor layer432 in Embodiment 1.

Note that before the oxide semiconductor layer 482 is formed by asputtering method, powdery substances (also referred to as particles ordust) which are generated at the time of the film formation and attachedon a surface of the gate insulating layer 452 are preferably removed byreverse sputtering in which an argon gas is introduced and plasma isgenerated.

Next, the oxide insulating film 457 which covers the gate insulatinglayer 452, the oxide semiconductor layer 482, the source electrode layer455 a, and the drain electrode layer 455 b and which is in contact withthe oxide semiconductor layer 482 is formed by a sputtering method or aPCVD method (see FIG. 4B). The oxide insulating film 457 can also beformed in a manner similar to that of the oxide insulating film 407described in Embodiment 1. In this embodiment, a silicon oxide filmhaving a thickness of 300 nm is formed as the oxide insulating film 457.The substrate temperature at the time of film formation may be higherthan or equal to a room temperature and lower than or equal to 300° C.,and the temperature is set at 100° C. in this embodiment.

Next, heat treatment is performed on the source electrode layer 455 a,the drain electrode layer 455 b, the gate insulating layer 452, theoxide insulating film 457, and the oxide semiconductor layer 482 underan oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium,neon, argon, or the like), or under reduced pressure, whereby the oxidesemiconductor layer 453 is formed (see FIG. 4C and FIG. 5B). The heattreatment is performed at a temperature of higher than or equal to 200°C. and lower than or equal to 700° C., preferably, higher than or equalto 350° C. and lower than the strain point of the substrate 450. Whenthe heat treatment is performed on the source electrode layer 455 a, thedrain electrode layer 455 b, the gate insulating layer 452, the oxideinsulating film 457, and the oxide semiconductor layer 453 under theabove atmosphere, impurities such as hydrogen and water included in thesource electrode layer 455 a, in the drain electrode layer 455 b, in thegate insulating layer 452, in the oxide insulating film 457, and in theoxide semiconductor layer 453, and at interfaces between the oxidesemiconductor layer 453 and upper and lower films which are in contactwith the oxide semiconductor layer 453 can be removed. In accordancewith conditions of the heat treatment or a material of the oxidesemiconductor layer, the oxide semiconductor layer is crystallized andchanged to a microcrystalline film or a polycrystalline film in somecases.

When the oxide insulating film 457 serving as a protective film isformed in contact with the oxide semiconductor layer 482, there is apossibility that the oxide semiconductor layer 482 might receive plasmadamage. However, with the heat treatment, plasma damage which is causedto the oxide semiconductor layer 482 can be repaired.

With this heat treatment, oxygen in the oxide insulating film 407 issupplied to the oxide semiconductor layer 403 using solid-phasediffusion. Accordingly, since the resistance of the oxide semiconductorlayer 403 increases, a highly reliable thin film transistor withfavorable electric characteristics can be manufactured.

The heat treatment can reduce variation in electric characteristics ofthe thin film transistor.

Note that in heat treatment for dehydration or dehydrogenation, it ispreferable that water, hydrogen, and the like be not contained innitrogen or a rare gas such as helium, neon, or argon. Alternatively, itis preferable that nitrogen or a rare gas such as helium, neon, or argonintroduced into an apparatus for heat treatment have purity of 6N(99.9999%) or more, preferably, 7N (99.99999%) or more, that is, animpurity concentration is set to 1 ppm or lower, preferably, 0.1 ppm orlower. After the heat treatment, slow cooling is preferably performedunder an oxygen atmosphere. For example, slow cooling may be performedso that the substrate temperature is lowered by at least approximately50° C. to 100° C. from the highest heating temperature.

As the heat treatment, an instantaneous heating method can be employed,such as a heating method using an electric furnace, a gas rapid thermalannealing (GRTA) method using a heated gas, or a lamp rapid thermalanneal (LRTA) method using lamp light.

Here, as an embodiment of heat treatment of the oxide semiconductorlayer 482, a heating method using an electric furnace 1601 will bedescribed with reference to FIG. 16.

FIG. 16 is a schematic view of the electric furnace 1601. Heaters 1603are provided outside a chamber 1602, which heats the chamber 1602.Inside the chamber 1602, a susceptor 1605 in which a substrate 1604 ismounted is provided. The substrate 1604 is transferred into/from thechamber 1602. In addition, the chamber 1602 is provided with a gassupply means 1606 and an evacuation means 1607. With the gas supplymeans 1606, a gas is introduced into the chamber 1602. The evacuationmeans 1607 exhausts the inside of the chamber 1602 or reduces thepressure in the chamber 1602. Note that the temperature risecharacteristics of the electric furnace 1601 are preferably set to from0.1° C./min to 20° C./min, inclusive. The temperature dropcharacteristics of the electric furnace 1601 are preferably set to from0.1° C./min to 15° C./min, inclusive.

The gas supply means 1606 includes a gas supply source 1611, a pressureregulation valve 1612, a refiner 1613, a mass flow controller 1614, anda stop valve 1615. In this embodiment, the refiner 1613 is preferablyprovided between the gas supply source 1611 and the chamber 1602. Therefiner 1613 can remove impurities such as water and hydrogen in a gaswhich is introduced into the chamber 1602 from the gas supply source1611; thus, entry into the chamber 1602 of water, hydrogen, and thelike, can be suppressed by provision of the refiner 1613.

In this embodiment, oxygen, nitrogen, or a rare gas is introduced intothe chamber 1602 from the gas supply source 1611, so that the inside ofthe chamber is in a nitrogen atmosphere or a rare gas atmosphere. In thechamber 1602 which is heated at a temperature of higher than or equal to200° C. and lower than or equal to 700° C., preferably, higher than orequal to 350° C. and lower than the strain point of the substrate 450,the oxide semiconductor layer formed over the substrate 450 is heated,whereby the oxide semiconductor layer can be subjected to dehydration ordehydrogenation.

Alternatively, the chamber 1602 in which the pressure is reduced by theevacuation means is heated at a temperature of higher than or equal to200° C. and lower than or equal to 700° C., preferably, higher than orequal to 350° C. and lower than the strain point of the substrate 450.In such a chamber 1602, the oxide semiconductor layer formed over thesubstrate 450 is heated, whereby the oxide semiconductor layer can besubjected to dehydration or dehydrogenation.

Next, the heaters are turned off, and the chamber 1602 of a heatingapparatus is gradually cooled.

As a result, reliability of the thin film transistor to be formed latercan be improved.

Note that when heat treatment is performed under reduced pressure, aninert gas may be introduced into the chamber 1602 after the heattreatment, pressure may be returned to atmospheric pressure, and coolingmay be performed.

After the substrate 1604 in the chamber 1602 of the heating apparatus iscooled to 300° C., the substrate 1604 may be transferred into anatmosphere at room temperature. As a result, the cooling time of thesubstrate 1604 can be shortened.

When the heating apparatus has a multi-chamber structure, heat treatmentand cooling treatment can be performed in chambers different from eachother. Typically, an oxide semiconductor layer over a substrate isheated in a first chamber that is filled with oxygen, nitrogen, or arare gas and heated at a temperature of higher than or equal to 200° C.and lower than or equal to 700° C., preferably, higher than or equal to350° C. and lower than the strain point of the substrate 450. Next, thesubstrate which has been subjected to the heat treatment is transferred,through the transfer chamber in which nitrogen or a rare gas isintroduced, into a second chamber that is filled with nitrogen or a raregas and heated at a temperature of lower than or equal to 100° C.,preferably at room temperature, and then cooling treatment is performedtherein. Through this process, throughput can be increased.

Although the oxide semiconductor layer 482 which has been subjected toheat treatment under an inert gas atmosphere or reduced pressure ispreferably an amorphous state, part of the oxide semiconductor layer 482may be crystallized.

As described above, when heat treatment is performed after the oxideinsulating film serving as a protective film is formed in contact withthe oxide semiconductor layer, impurities (H₂O, H, OH, or the like)included in the source electrode layer, the drain electrode layer, thegate insulating layer, the oxide insulating film, and the oxidesemiconductor layer can be reduced. With the heat treatment, plasmadamage which is caused to the oxide semiconductor layer when the oxideinsulating film serving as a protective film is formed in contact withthe oxide semiconductor layer can be repaired. The heat treatment canreduce variation in electric characteristics of the thin filmtransistor. Accordingly, electric characteristics and reliability of thethin film transistor 460 can be improved.

Next, the first contact hole 471, the second contact hole 472, the thirdcontact hole 473, and the fourth contact hole 474 are formed in theoxide insulating film 457 (see FIG. 4D and FIG. 5C). First, when part ofthe oxide insulating film 457 is removed by etching, the first contacthole 471 which reaches the source electrode layer 455 a, part of thesecond contact hole 472 which reaches the gate electrode layer 451, andthe third contact hole 473 and the fourth contact hole 474 which reachboth end portions of the connection electrode layer 470 are formed.Further, part of the gate insulating layer 452 is removed by etching, sothat the second contact hole which reaches the gate electrode layer 451is formed.

Next, a second conductive film is formed over the oxide insulating film457. Here, the second conductive film is connected to the sourceelectrode layer 455 a, the gate electrode layer 451, and the connectionelectrode layer 470 through the first contact hole 471, the secondcontact hole 472, the third contact hole 473, and the fourth contacthole 474.

The second conductive film is preferably formed using a low resistanceconductive material which has lower resistivity than the sourceelectrode layer 455 a and the drain electrode layer 455 b, and aluminumor copper is particularly preferable. With the use of the low resistanceconductive material for the second conductive film, wiring resistance orthe like can be reduced.

Although the low resistance conductive material such as aluminum orcopper has low heat resistivity, the second conductive film can beprovided after the heat treatment; therefore, the low resistanceconductive material such as aluminum or copper can be used.

Next, the second conductive film is etched through an etching process,so that the source wiring 475, the first gate wiring 476, and the secondgate wiring 477 are formed over the oxide insulating film 457 (see FIG.4E and FIG. 5D). The source wiring 475 is formed so as to overlap theconnection electrode layer 470 and so as to be connected to the sourceelectrode layer 455 a through the first contact hole 471. The first gatewiring 476 and the second gate wiring 477 are formed so as to sandwichthe source wiring 475 therebetween. Here, the first gate wiring 476 isformed so as to be connected to the gate electrode layer 451 through thesecond contact hole 472 and so as to be connected to the connectionelectrode layer 470 through the third contact hole 473. The second gatewiring 477 is formed so as to be connected to the connection electrodelayer 470 through the fourth contact hole 474. Accordingly, the firstgate wiring 476 and the second gate wiring 477 are electricallyconnected to each other through the connection electrode layer 470.

Through the above process, the thin film transistor 460 can be formed.The structures illustrated in FIGS. 6C and 6D can be manufactured in asimilar process.

As described above, when heat treatment is performed after the oxideinsulating film serving as a protective film is formed in contact withthe oxide semiconductor layer, impurities (H₂O, H, OH, or the like)included in the source electrode layer, the drain electrode layer, thegate insulating layer, and the oxide semiconductor layer can be reduced.With the heat treatment, plasma damage which is caused to the oxidesemiconductor layer when the oxide insulating film serving as aprotective film is formed in contact with the oxide semiconductor layercan be repaired. The heat treatment can reduce variation in electriccharacteristics of the thin film transistor. Therefore, reliability ofthe thin film transistor 460 can be improved.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 3

A manufacturing process of a semiconductor device including a thin filmtransistor will be described with reference to FIGS. 7A to 7D, FIGS. 8Ato 8C, FIGS. 9A and 9B, FIG. 10, FIG. 11, FIG. 12, and FIG. 13. FIGS. 7Ato 7D, FIGS. 8A to 8C, and FIGS. 9A and 9B are cross-sectional views ofa manufacturing process, and FIG. 10, FIG. 11, FIG. 12, and FIG. 13 areplan views of the manufacturing process.

As for a substrate 100 having a light-transmitting property illustratedin FIG. 7A, a glass substrate of barium borosilicate glass,aluminoborosilicate glass, or the like can be used. Note that asubstrate formed of an insulator such as a ceramic substrate, a quartzglass substrate, a quartz substrate, or a sapphire substrate may be usedinstead of the glass substrate 100. Alternatively, crystallized glass orthe like may be used.

Next, a conductive layer is formed over the entire surface of thesubstrate 100, and then a first photolithography process is performed toform a resist mask. Then, an unnecessary portion is removed by etching,so that a wiring and an electrode (a gate electrode layer 101, acapacitor wiring 108, and a first terminal 121) are formed. At thistime, the etching is performed so that at least end portions of the gateelectrode layer 101 have a tapered shape.

The gate electrode layer 101, the capacitor wiring 108, and the firstterminal 121 of a terminal portion can be formed using the material ofthe gate electrode layer 401 described in Embodiment 1, as appropriate.Each of the gate electrode layer 101, the capacitor wiring 108, and thefirst terminal 121 of the terminal portion is preferably formed using aheat-resistance conductive material in order to endure heat treatment ina later step, and is formed using an element selected from titanium(Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr),neodymium (Nd), or scandium (Sc); an alloy including any of theseelements as a component; an alloy film including any of these elementsas a component in combination; or a nitride including any of theseelements as a component, in a single layer or a stacked layer.

At this time, a connection electrode layer 220 which is formed at thesame time as the formation of a source electrode layer 105 a and a drainelectrode layer 105 b which are formed in a later step may be formed atthe same time as the formation of the gate electrode layer 101. In thatcase, the connection electrode layer 220 is not necessarily formed whenthe source electrode layer 105 a and the drain electrode layer 105 b areformed.

Next, a gate insulating layer 102 is formed over the entire surface ofthe gate electrode layer 101. The gate insulating layer 102 is formed toa thickness of 50 to 250 nm by a sputtering method, a PCVD method, orthe like.

For example, as the gate insulating layer 102, a silicon oxide film isformed to a thickness of 100 nm by a sputtering method. Needless to say,the gate insulating layer 102 is not limited to such as a silicon oxidefilm and may be formed to have a single-layer structure or a stackedstructure using another insulating film such as a silicon oxynitridefilm, a silicon nitride film, an aluminum oxide film, a tantalum oxidefilm, and the like.

Next, an oxide semiconductor film (In—Ga—Zn—O-based non-single-crystalfilm) is formed over the gate insulating layer 102. It is effective todeposit the In—Ga—Zn—O-based non-single-crystal film without exposure toair after the plasma treatment because dust and moisture are notattached to the interface between the gate insulating layer and thesemiconductor film. Here, the oxide semiconductor film is formed in anoxygen atmosphere, an argon atmosphere, or an atmosphere containingargon and oxygen under the condition where a target is an oxidesemiconductor target containing In, Ga, and Zn (In—Ga—Zn—O-based oxidesemiconductor target (In₂O₃:Ga₂O₃:ZnO=1:1:1)) with a diameter of 8inches, the distance between the substrate and the target is 170 mm, thepressure is 0.4 Pa, and the direct current (DC) power supply is 0.5 kW.Note that a pulse direct current (DC) power supply is preferable becausedust can be reduced and the film thickness can be uniform. TheIn—Ga—Zn—O-based non-single-crystal film is formed to a thickness of 5nm to 200 nm. As the oxide semiconductor film, an In—Ga—Zn—O-basednon-single-crystal film with a thickness of 50 nm is formed using theIn—Ga—Zn—O-based oxide semiconductor target by a sputtering method.

Examples of a sputtering method include an RF sputtering method in whicha high-frequency power supply is used for a sputtering power supply, aDC sputtering method, and a pulsed DC sputtering method in which a biasis applied in a pulsed manner. An RF sputtering method is mainly used inthe case where an insulating film is formed, and a DC sputtering methodis mainly used in the case where a metal film is formed.

In addition, there is also a multi-source sputtering apparatus in whicha plurality of targets of different materials can be set. With themulti-source sputtering apparatus, films of different materials can bedeposited to be stacked in the same chamber, and a film of plural kindsof materials can be deposited by electric discharge at the same time inthe same chamber.

In addition, there are a sputtering apparatus provided with a magnetsystem inside the chamber and used for a magnetron sputtering method,and a sputtering apparatus used for an ECR sputtering method in whichplasma generated with the use of microwaves is used without using glowdischarge.

In addition, as a film formation method using a sputtering method, thereare also a reactive sputtering method in which a target substance and asputtering gas component are chemically reacted with each other duringfilm formation to form a thin film of a compound thereof, and a biassputtering method in which voltage is also applied to a substrate duringfilm formation.

Next, a second photolithography process is performed to form a resistmask, and then the oxide semiconductor film is etched. For example,unnecessary portions are removed by wet etching using a mixed solutionof phosphoric acid, acetic acid, and nitric acid, so that an oxidesemiconductor layer 133 is formed (see FIG. 7A and FIG. 10). Note thatetching here is not limited to wet etching and dry etching may also beperformed.

As the etching gas for dry etching, a gas containing chlorine(chlorine-based gas such as chlorine (Cl₂), boron chloride (BCl₃),silicon chloride (SiCl₄), or carbon tetrachloride (CCl₄)) is preferablyused.

Alternatively, a gas containing fluorine (fluorine-based gas such ascarbon tetrafluoride (CF₄), sulfur hexafluoride (SF₆), nitrogentrifluoride (NF₃), or trifluoromethane (CHF₃)); oxygen (O₂); any ofthese gases to which a rare gas such as helium (He) or argon (Ar) isadded; or the like can be used as the etching gas used for dry etching.

As the dry etching method, a parallel plate reactive ion etching (RIE)method, an inductively coupled plasma (ICP) etching method, or the likecan be used. In order to etch the films into desired shapes, the etchingcondition (the amount of electric power applied to a coil-shapedelectrode, the amount of electric power applied to an electrode on asubstrate side, the temperature of the electrode on the substrate side,or the like) is adjusted as appropriate.

As an etchant used for wet etching, a solution obtained by mixingphosphoric acid, acetic acid, and nitric acid or the like can be used.In addition, ITO07N (produced by KANTO CHEMICAL CO., INC.) may also beused.

The etchant used in the wet etching is removed by cleaning together withthe material which is etched off. The waste liquid including the etchantand the material etched off may be purified and the material may bereused. When a material such as indium included in the oxidesemiconductor layer is collected from the waste liquid after the etchingand reused, the resources can be efficiently used and the cost can bereduced.

Note that the etching condition (etching solution, etching time,temperature, or the like) are adjusted as appropriate, depending on amaterial, so that the films can be etched into the desired shapes.

Then, a first conductive film 132 made of a metal material is formedover the oxide semiconductor layer 133 by a sputtering method or avacuum evaporation method (see FIG. 7B).

For a material of the first conductive film 132, a material which issimilar to that of the source electrode layer 405 a and the drainelectrode layer 405 b described in Embodiment 1 can be used asappropriate. The first conductive film 132 is preferably formed using aheat-resistance conductive material in order to endure heat treatment ina later step, and is formed using an element selected from titanium(Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr),neodymium (Nd), or scandium (Sc); an alloy including any of theseelements as a component; an alloy film including any of these elementsas a component in combination; or a nitride including any of theseelements as a component, in a single layer or a stacked layer.

For the heat resistant conductive material used for the first conductivefilm 132, a transparent conductive oxide containing any of indium, tin,or zinc may be used. For example, indium oxide (In₂O₃) or an indiumoxide-tin oxide (In₂O₃—SnO₂, abbreviated to ITO) alloy is preferablyused. Alternatively, a transparent conductive oxide to which aninsulating oxide such as silicon oxide is added may be used.

By inclusion of the insulating oxide such as silicon oxide in thetransparent conductive oxide, crystallization of the transparentconductive oxide can be suppressed and the transparent conductive oxidecan have an amorphous structure. Crystallization of the transparentconductive oxide is suppressed and an amorphous structure is provided,so that crystallization of the transparent conductive oxide orgeneration of microcrystalline grains can be prevented even when heattreatment is performed.

Next, a third photolithography process is performed. A resist mask isformed, and unnecessary portions are removed by etching, whereby thesource electrode layer 105 a, the drain electrode layer 105 b, theconnection electrode layer 220, and a second terminal 122 are formed(see FIG. 7C and FIG. 11). Wet etching or dry etching is employed as anetching method at this time. For example, by wet etching using anammonia hydrogen peroxide mixture (with the ratio of hydrogenperoxide:ammonia:water=5:2:2), the first conductive film 132 may beetched to form the source electrode layer 105 a and the drain electrodelayer 105 b. In this etching step, an exposed region of the oxidesemiconductor layer 133 is partly etched to be an oxide semiconductorlayer 135. Therefore, a region of the oxide semiconductor layer 135,which lies between the source electrode layer 105 a and the drainelectrode layer 105 b has a small thickness. The region with a smallthickness has a thickness of approximately 30 nm which further hinderscrystallization; therefore, the region with a small thickness iseffective in the case where a portion serving as a channel is desired tobe kept to be in an amorphous state. In FIG. 7C, the etching for formingthe source electrode layer 105 a, the drain electrode layer 105 b, andthe oxide semiconductor layer 135 is performed at a time by dry etching.Accordingly, end portions of the source electrode layer 105 a and thedrain electrode layer 105 b are aligned with end portions of the oxidesemiconductor layer 135; thus, continuous structures are formed.

In the third photolithography process, the second terminal 122 which isformed using the same material as the source electrode layer 105 a andthe drain electrode layer 105 b is left in a terminal portion. Note thatthe second terminal 122 is electrically connected to a source wiring tobe formed in a later step.

When the connection electrode layer 420 is formed at the same time asthe formation of the gate electrode layer 401, the connection electrodelayer 420 is not necessarily formed here.

Further, by use of a resist mask having regions with plural thicknesses(typically, two different thicknesses) which is formed using amulti-tone mask, the number of resist masks can be reduced, resulting insimplified process and lower costs.

Then, the resist mask is removed, and a protective insulating layer 107is formed to cover the gate insulating layer 102, the oxidesemiconductor layer 135, the source electrode layer 105 a, and the drainelectrode layer 105 b (see FIG. 7D). The protective insulating layer 107can be formed to a thickness of at least 1 nm or more using a method bywhich impurities such as water and hydrogen are prevented from beingmixed to the protective insulating layer 107, such as a CVD method or asputtering method, as appropriate. Here, the protective insulating layer107 is formed using a sputtering method. The protective insulating layer107 which is in contact with part of the oxide semiconductor layer 135does not include impurities such as moisture, hydrogen ions, and OH⁻,and is formed using an inorganic insulating film which prevents entry ofthese from the outside. Specifically, a silicon oxide film, a siliconnitride oxide film, an aluminum oxide film, or an aluminum oxynitridefilm is used. Further, a silicon nitride film or an aluminum nitridefilm may be stacked so as to be formed over and in contact with theprotective insulating layer 107. The silicon nitride film does notinclude impurities such as moisture, hydrogen ions, and OW and preventsentry of these from the outside.

When the protective insulating layer 107 is formed in contact with theoxide semiconductor layer 135 by a sputtering method, a PCVD method, orthe like, a region of the oxide semiconductor layer 135, which is incontact with at least the protective insulating layer 107 can be of highresistance (carrier concentration is decreased, preferably, the carrierconcentration is less than 1×10¹⁸/cm³), and can serve as ahigh-resistance oxide semiconductor region.

Next, heat treatment is performed on the source electrode layer 105 a,the drain electrode layer 105 b, the gate insulating layer 102, and theoxide semiconductor layer 135 under an oxygen gas atmosphere, an inertgas atmosphere (nitrogen, helium, neon, argon, or the like), or underreduced pressure, whereby an oxide semiconductor layer 103 is formed(see FIG. 8A). The heat treatment is performed at a temperature ofhigher than or equal to 200° C. and lower than or equal to 700° C.,preferably, higher than or equal to 350° C. and lower than the strainpoint of the substrate 100. When the heat treatment is performed on thesource electrode layer 105 a, the drain electrode layer 105 b, the gateinsulating layer 102, and the oxide semiconductor layer 103 under theabove atmosphere, impurities such as hydrogen and water included in thesource electrode layer 105 a, in the drain electrode layer 105 b, in thegate insulating layer 102, and in the oxide semiconductor layer 103, andat interfaces between the oxide semiconductor layer 103 and upper andlower films which are in contact with the oxide semiconductor layer 103can be removed. In accordance with conditions of the heat treatment or amaterial of the oxide semiconductor layer, the oxide semiconductor layeris crystallized and changed to a microcrystalline film or apolycrystalline film in some cases.

When the protective insulating layer 107 serving as a protective film isformed in contact with the oxide semiconductor layer 133, there is apossibility that the oxide semiconductor layer 133 might receive plasmadamage. However, with the heat treatment, plasma damage which is causedto the oxide semiconductor layer 133 can be repaired.

With this heat treatment, oxygen in the protective insulating layer 107is supplied to the oxide semiconductor layer 103 using solid-phasediffusion. Accordingly, since the resistance of the oxide semiconductorlayer 103 increases, a highly reliable thin film transistor withfavorable electric characteristics can be manufactured.

The heat treatment can reduce variation in electric characteristics ofthe thin film transistor. After the heat treatment, slow cooling ispreferably performed under an oxygen atmosphere. For example, slowcooling may be performed so that the substrate temperature is lowered byat least approximately 50° C. to 100° C. from the highest heatingtemperature.

Next, a fourth photolithography process is performed. A resist mask isformed, and the protective insulating layer 107 and the gate insulatinglayer 102 are etched to form a first contact hole 221, a second contacthole 222, a third contact hole 223, and a fourth contact hole 224 (seeFIG. 8B and FIG. 12). First, when part of the protective insulatinglayer 107 is removed by etching, the first contact hole 221 whichreaches the source electrode layer 105 a, part of the second contacthole 222 which reaches the gate electrode layer 101, and the thirdcontact hole 223 and the fourth contact hole 224 which reach both endportions of the connection electrode layer 220 are formed. Further, partof the gate insulating layer 102 is removed by etching, so that thesecond contact hole 222 which reaches the gate electrode layer 101 isformed.

When a reflective display device is manufactured, a contact hole whichreaches the drain electrode layer 105 b may be formed here, and a pixelelectrode layer 110 may be formed at the same time as the formation of asource wiring and a gate wiring.

Next, a second conductive film made of a metal material is formed overthe protective insulating layer 107 by a sputtering method or a vacuumevaporation method. Here, the second conductive film is connected to thesource electrode layer 105 a, the gate electrode layer 101, and theconnection electrode layer 220 through the first contact hole 221, thesecond contact hole 222, the third contact hole 223, and the fourthcontact hole 224.

As a material for the second conductive film, a material which issimilar to that of the second conductive film described in Embodiment 1can be used as appropriate. The second conductive film is preferablyformed using a low resistance conductive material which has lowerresistivity than the source electrode layer 105 a and the drainelectrode layer 105 b, and aluminum or copper is particularlypreferable. With the use of the low resistance conductive material forthe second conductive film, wiring resistance or the like can bereduced.

Next, a fifth photolithography process is performed. A resist mask isformed, and the second conductive film is etched to form a source wiring225, a first gate wiring 226, and a second gate wiring 227 over theprotective insulating layer 107 (see FIG. 8C and FIG. 12). The sourcewiring 225 overlaps the connection electrode layer 220 and is formed soas to be connected to the source electrode layer 105 a through the firstcontact hole 221. The first gate wiring 226 and the second gate wiring227 are formed so as to sandwich the source wiring 225. Here, the firstgate wiring 226 is formed so as to be connected to the gate electrodelayer 101 through the second contact hole 222 and so as to be connectedto the connection electrode layer 220 through the third contact hole223. In addition, the second gate wiring 227 is formed so as to beconnected to the connection electrode layer 220 through the fourthcontact hole 224. Accordingly, the first gate wiring 226 and the secondgate wiring 427 are electrically connected to each other through theconnection electrode layer 220.

Through the above steps, a thin film transistor 170 can be manufactured.

Next, a sixth photolithography process is performed. A resist mask isformed, and the protective insulating layer 107 is etched to form acontact hole 125 which reaches the drain electrode layer 105 b. Inaddition, a contact hole 127 which reaches the second terminal 122 and acontact hole 126 which reaches the first terminal 121 are also formed inthe same etching step. A cross-sectional view at this stage isillustrated in FIG. 9A. Note that the contact hole 125, the contact hole126, and the contact hole 127 can be formed at the same time in thefourth photolithography process.

Next, the resist mask is removed, and then a transparent conductive filmis formed. The transparent conductive film is formed using indium oxide(In₂O₃), an indium oxide-tin oxide (In₂O₃—SnO₂, abbreviated as ITO)alloy, or the like by a sputtering method, a vacuum evaporation method,or the like. Such a material is etched with a hydrochloric acid-basedsolution. However, since a residue is easily generated particularly inetching ITO, indium oxide-zinc oxide alloy (In₂O₃—ZnO) may be used toimprove etching processability. When heat treatment for reducing theresistance of the transparent conductive film is performed, an increasein the resistance of the oxide semiconductor layer 103 and improvementand less variation in electric characteristics of the transistor can beachieved.

Next, a seventh photolithography process is performed. A resist mask isformed, and an unnecessary portion is removed by etching to form thepixel electrode layer 110.

Further, in this seventh photolithography process, the capacitor wiring108 and the pixel electrode layer 110 together form a storage capacitorwith the use of the gate insulating layer 102 and the protectiveinsulating layer 107 in a capacitor portion as a dielectric.

In addition, in this seventh photolithography process, the firstterminal 121 and the second terminal 122 are covered with the resistmask, and transparent conductive films 128 and 129 are left in theterminal portions. The transparent conductive films 128 and 129 functionas electrodes or wirings connected to an FPC. The transparent conductivefilm 128 formed over the first terminal 121 is a connection terminalelectrode which functions as an input terminal of the gate wiring. Thetransparent conductive film 129 formed over the second terminal 122 is aconnection terminal electrode which functions as an input terminal ofthe source wiring.

Then, the resist mask is removed, and a cross-sectional view at thisstage is illustrated in FIG. 9B. Note that a top view at this stagecorresponds to FIG. 13.

Further, FIGS. 14A and 14B are a cross-sectional view of a gate wiringterminal portion at this stage and a plan view thereof, respectively.FIG. 14A corresponds to a cross-sectional view taken along E1-E2 of FIG.14B. In FIG. 14A, a transparent conductive film 155 formed over aprotective insulating film 154 is a connection terminal electrode whichfunctions as an input terminal. In the terminal portion in FIG. 14A, afirst terminal 151 formed using the same material as the material of thegate wiring and a connection electrode layer 153 formed using the samematerial as the material of the source wiring overlap each other with agate insulating layer 152 interposed therebetween and are electricallyconnected through the transparent conductive film 155. Note that aportion where the transparent conductive film 128 and the first terminal121 are in contact with each other as illustrated in FIG. 9B correspondsto a portion where the transparent conductive film 155 and the firstterminal 151 are in contact with each other in FIG. 14A.

FIGS. 14C and 14D are respectively a cross-sectional view and a top viewof a source wiring terminal portion which is different from thatillustrated in FIG. 9B. FIG. 14C is a cross-sectional view taken alongline F1-F2 of FIG. 14D. In FIG. 14C, the transparent conductive film 155formed over the protective insulating film 154 is a connection terminalelectrode which functions as an input terminal. In the terminal portionin FIG. 14C, an electrode layer 156 formed using the same material asthe gate wiring is located under a second terminal 150, which iselectrically connected to the source wiring, with the gate insulatinglayer 152 interposed therebetween. The electrode layer 156 is notelectrically connected to the second terminal 150, and a capacitor forpreventing noise or static electricity can be formed when the potentialof the electrode layer 156 is set to a potential different from that ofthe second terminal 150, such as floating, GND, or 0 V. The secondterminal 150 is electrically connected to the transparent conductivefilm 155 through the protective insulating film 154.

A plurality of gate wirings, source wirings, and capacitor wirings areprovided depending on the pixel density. Also in the terminal portion,the first terminal at the same potential as the gate wiring, the secondterminal at the same potential as the source wiring, the third terminalat the same potential as the capacitor wiring, and the like are eacharranged in plurality. The number of each of the terminals may be anynumber, and the number of the terminals may be determined by apractitioner, as appropriate.

Through these seven photolithography processes, the storage capacitorand a pixel thin film transistor portion including the thin filmtransistor 170 of a bottom-gate staggered thin film transistor can becompleted using the seven photomasks. By disposing the thin filmtransistor and the storage capacitor in each pixel of a pixel portion inwhich pixels are arranged in a matrix, one of substrates formanufacturing an active matrix display device can be obtained. In thisspecification, such a substrate is referred to as an active matrixsubstrate for convenience.

In the case of manufacturing an active matrix liquid crystal displaydevice, an active matrix substrate and a counter substrate provided witha counter electrode are bonded to each other with a liquid crystal layerinterposed therebetween. Note that a common electrode electricallyconnected to the counter electrode on the counter substrate is providedover the active matrix substrate, and a fourth terminal electricallyconnected to the common electrode is provided in the terminal portion.The fourth terminal is provided so that the common electrode is set to afixed potential such as GND or 0 V.

A capacitor wiring is not provided, and a pixel electrode overlaps agate wiring of an adjacent pixel with a protective insulating film and agate insulating layer interposed therebetween to form a storagecapacitor.

In an active matrix liquid crystal display device, pixel electrodesarranged in a matrix are driven to form a display pattern on a screen.Specifically, voltage is applied between a selected pixel electrode anda counter electrode corresponding to the pixel electrode, so that aliquid crystal layer provided between the pixel electrode and thecounter electrode is optically modulated and this optical modulation isrecognized as a display pattern by an observer.

In displaying moving images, a liquid crystal display device has aproblem that a long response time of liquid crystal molecules themselvescauses afterimages or blurring of moving images. In order to improve themoving-image characteristics of a liquid crystal display device, adriving method called black insertion is employed in which black isdisplayed on the whole screen every other frame period.

Alternatively, a driving method called double-frame rate driving may beemployed in which the vertical synchronizing frequency is 1.5 times ormore, preferably twice or more as high as a usual vertical synchronizingfrequency, whereby the moving-image characteristics are improved.

Further alternatively, in order to improve the moving-imagecharacteristics of a liquid crystal display device, a driving method maybe employed, in which a plurality of LED (light-emitting diode) lightsources or a plurality of EL light sources are used to form a surfacelight source as a backlight, and each light source of the surface lightsource is independently driven in a pulsed manner in one frame period.As the surface light source, three or more kinds of LEDs may be used andan LED emitting white light may be used. Since a plurality of LEDs canbe controlled independently, the light emission timing of LEDs can besynchronized with the timing at which a liquid crystal layer isoptically modulated. According to this driving method, LEDs can bepartly turned off; therefore, an effect of reducing power consumptioncan be obtained particularly in the case of displaying an image having alarge part on which black is displayed.

By combining these driving methods, the display characteristics of aliquid crystal display device, such as moving-image characteristics, canbe improved as compared to those of conventional liquid crystal displaydevices.

The n-channel transistor disclosed in this specification includes anoxide semiconductor film which is used for a channel formation regionand has excellent dynamic characteristics; thus, it can be combined withthese driving techniques.

In manufacturing a light-emitting display device, one electrode (alsoreferred to as a cathode) of an organic light-emitting element is set toa low power supply potential such as GND or 0 V; thus, a terminalportion is provided with a fourth terminal for setting the cathode to alow power supply potential such as GND or 0 V. Also in manufacturing alight-emitting display device, a power supply line is provided inaddition to a source wiring and a gate wiring. Accordingly, the terminalportion is provided with a fifth terminal electrically connected to thepower supply line.

When a light-emitting display device is manufactured, a partition formedusing an organic resin layer is provided between organic light-emittingelements in some cases. In that case, heat treatment performed on theorganic resin layer can also serve as the heat treatment which increasesthe resistance of the oxide semiconductor layer 103 so that improvementand less variation in electric characteristics of the transistor areachieved.

By the heat treatment, impurities such as moisture are reduced and thepurity of the oxide semiconductor film is increased. Therefore, asemiconductor device including a highly reliable thin film transistorhaving favorable electric characteristics can be manufactured withoutusing a special sputtering apparatus in which dew point in a filmformation chamber is lowered or an ultrapure oxide semiconductor target.

The channel formation region in the oxide semiconductor layer is ahigh-resistance region; thus, electric characteristics of the thin filmtransistor are stabilized and increase in off current can be prevented.Therefore, a semiconductor device including a highly reliable thin filmtransistor having favorable electric characteristics can be provided.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 4

A semiconductor device and a method for manufacturing the semiconductordevice will be described with reference to FIG. 17. The same portion asEmbodiment 1 or a portion having similar function to that described inEmbodiment 1 and a process can be formed in a manner similar to thatdescribed in Embodiment 1; therefore, repetitive description is omitted.

In a thin film transistor 462 illustrated in FIG. 17, a conductive layer409 is provided from the same layer as the source wiring 425 over theoxide insulating film 407 so that the conductive layer 409 overlaps thegate electrode layer 401 and a channel region of the oxide semiconductorlayer 403.

FIG. 17 is a cross-sectional view of the thin film transistor 462included in a semiconductor device. The thin film transistor 462 is abottom-gate thin film transistor and includes the gate electrode layer401, the gate insulating layer 402, the oxide semiconductor layer 403,the source electrode layer 405 a, the drain electrode layer 405 b, theoxide insulating film 407, the source wiring 425, and the conductivelayer 409, over the substrate 400 having an insulating surface. Theconductive layer 409 is provided over the oxide insulating film 407 sothat the conductive layer 409 overlaps the gate electrode layer 401.Although not illustrated in FIG. 17, a gate wiring and a connectionelectrode layer are also provided in a manner similar to that ofEmbodiment 1.

The conductive layer 409 can be formed using a material and a methodwhich are similar to those of the source wiring 425 described inEmbodiment 1. When a pixel electrode layer is provided, the conductivelayer may be formed using a material and a method which are similar tothose of the pixel electrode layer. In this embodiment, a low resistanceconductive material such as aluminum or copper is used for theconductive layer 409.

The potential of the conductive layer 409 may be the same as ordifferent from the potential of the gate electrode layer 401, and canfunction as a second gate electrode layer. Further, the conductive layer409 may be in a floating state.

The conductive layer 409 is provided in a position that overlaps theoxide semiconductor layer 403, whereby in a bias-temperature stress test(hereinafter, referred to as a BT test) for examining reliability of thethin film transistor, the amount of change in threshold voltage of thethin film transistor 462 between before and after the BT test can bereduced. In particular, in a −BT test in which voltage applied to a gateis set at −20 V after the substrate temperature is raised to 150° C.,variations in threshold voltage can be suppressed.

This embodiment can be freely combined with Embodiment 1.

Embodiment 5

A semiconductor device and a method for manufacturing the semiconductordevice will be described with reference to FIG. 18. The same portion asEmbodiment 1 or a portion having similar function to that described inEmbodiment 1 and a process can be formed in a manner similar to thatdescribed in Embodiment 1; therefore, repetitive description is omitted.

A thin film transistor 463 illustrated in FIG. 18 includes a conductivelayer 419 with the oxide insulating film 407 and an insulating layer 410interposed between the conductive layer 419 and the gate electrode layer401 so that the conductive layer 419 overlaps the gate electrode layer401 and the channel region of the oxide semiconductor layer 403.

FIG. 18 is a cross-sectional view of the thin film transistor 463included in a semiconductor device. The thin film transistor 463 is abottom-gate thin film transistor, and includes the gate electrode layer401, the gate insulating layer 402, the oxide semiconductor layer 403, asource region 404 a, a drain region 404 b, the source electrode layer405 a, the drain electrode layer 405 b, the oxide insulating film 407,the insulating layer 410, the source wiring 425, and the conductivelayer 419, over the substrate 400 having an insulating surface. Theconductive layer 419 is provided over the insulating layer 410 so thatthe conductive layer 419 overlaps the gate electrode layer 401. Althoughnot illustrated in FIG. 18, a gate wiring and a connection electrodelayer are also provided in a manner similar to that of Embodiment 1.

In this embodiment, after an oxide semiconductor layer is formed overthe gate insulating layer 402, the source region 404 a and the drainregion 404 b are formed over the oxide semiconductor layer. Then, thesource electrode layer 405 a and the drain electrode layer 405 b areformed, and the oxide insulating film 407 is formed. In a manner similarto that of Embodiment 1, after the oxide insulating film 407 is formed,heat treatment for dehydration or dehydrogenation is performed, and theoxide semiconductor layer 403 is formed. The heat treatment is performedat a temperature of higher than or equal to 200° C. and lower than orequal to 700° C., preferably, higher than or equal to 350° C. and lowerthan the strain point of the substrate 400 under an oxygen gasatmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, orthe like), or under reduced pressure. Slow cooling is preferablyperformed under an inert gas atmosphere or an oxygen atmosphere afterthe heat treatment. The heat treatment allows plasma damage caused whenthe oxide insulating film 407 is formed to be repaired. Then, a contacthole is formed in the oxide insulating film 407, and the source wiring425 which is connected to the source electrode layer 405 a is formed.

In this embodiment, the source region 404 a and the drain region 404 bare each formed using a Zn—O-based polycrystalline film or a Zn-basedmicrocrystalline film and are formed under a film formation conditionwhich is different from that of the oxide semiconductor layer 403 andeach have lower resistance than oxide semiconductor layer 403. In thisembodiment, the source region 404 a and the drain region 404 b are in apolycrystalline state or a microcrystalline state, and the oxidesemiconductor layer 403 is also in a polycrystalline state or amicrocrystalline state. The oxide semiconductor layer 403 iscrystallized with the second heat treatment, so that the oxidesemiconductor layer 403 can be in a polycrystalline state or amicrocrystalline state.

In the thin film transistor described in this embodiment, the insulatinglayer 410 functioning as a planarization film is stacked over the oxideinsulating film 407, an opening which reaches the drain electrode layer405 b is formed in the oxide insulating film 407 and the insulatinglayer 410, and a conductive film is formed in the opening formed in theoxide insulating film 407 and the insulating layer 410, and theconductive film is etched to have a predetermined shape, whereby theconductive layer 419 and a pixel electrode layer 411 are formed. In sucha process in which the pixel electrode layer 411 is formed, theconductive layer 419 can be formed. In this embodiment, as the pixelelectrode layer 411 and the conductive layer 419, an indium oxide-tinoxide alloy including silicon oxide (In—Sn—O-based oxide containingsilicon oxide) is used.

Alternatively, the conductive layer 419 may be formed using a materialand a manufacturing method which are similar to that of the gateelectrode layer 401, the source electrode layer 405 a, the drainelectrode layer 405 b, and the source wiring 425.

The potential of the conductive layer 419 may be the same as ordifferent from that of the gate electrode layer 401. The conductivelayer 419 can function as a second gate electrode layer. Further, theconductive layer 419 may be in a floating state.

When the conductive layer 419 is provided so as to overlap the oxidesemiconductor layer 403, the threshold voltage of the thin filmtransistor 463 can be controlled.

This embodiment can be freely combined with Embodiment 1.

Embodiment 6

In this embodiment, an example of a channel stop type thin filmtransistor 1430 will be described with reference to FIGS. 19A, 19B, and19C. FIG. 19C is an example of a top view of a thin film transistor, across-sectional view taken along dotted line Z1-Z2 of which correspondsto FIG. 19B. An example is described in which gallium is not containedin an oxide semiconductor layer of the thin film transistor 1430.

In FIG. 19A, a gate electrode layer 1401 is formed over a substrate1400. Here, the gate electrode layer is preferably formed using a heatresistant conductive material such as that described in Embodiment 1 sothat the gate electrode layer can endure heat treatment to be performedin a later step. Next, a gate insulating layer 1402 covering the gateelectrode layer 1401 is formed. Then, an oxide semiconductor layer 1403is formed over the gate insulating layer 1402.

In this embodiment, as the oxide semiconductor layer 1403, aSn—Zn—O-based oxide semiconductor formed using a sputtering method isused. When gallium is not used for the oxide semiconductor layer, theoxide semiconductor layer 1403 can be formed without expensive target,so that cost can be reduced.

Next, a channel protective layer 1418 is formed in contact with theoxide semiconductor layer 1403. The formation of the channel protectivelayer 1418 over the oxide semiconductor layer 1403 can prevent damage(reduction in thickness or the like due to plasma or an etchant inetching) in a later step of forming a source region 1406 a and a drainregion 1406 b. Therefore, reliability of the thin film transistor 1430can be improved.

Alternatively, after the oxide semiconductor layer 1403 is formed, thechannel protective layer 1418 can be successively formed withoutexposure to air. Successive treatment without exposure to air makes itpossible to obtain each interface of stacked layers, which are notcontaminated by atmospheric components or impurity elements floating inair, such as water or hydrocarbon. Therefore, variation incharacteristics of the thin film transistor can be reduced.

The channel protective layer 1418 can be formed using an inorganicmaterial containing oxygen (such as silicon oxide, silicon oxynitride,or silicon nitride oxide). As a method for forming the channelprotective layer 1418, a vapor deposition method such as a plasmaenhanced CVD method or a thermal CVD method, or a sputtering method canbe used. After the formation of the channel protective layer 1418, theshape thereof is processed by etching. Here, the channel protectivelayer 1418 is formed in such a manner that a silicon oxide film isformed by a sputtering method and processed by etching using a maskformed by photolithography.

Next, the source region 1406 a and the drain region 1406 b are formedover the channel protective layer 1418 and the oxide semiconductor layer1403. In this embodiment, the source region 1406 a and the drain region1406 b are each formed using a Zn—O-based microcrystalline film or aZn—O-based polycrystalline film and are formed under a film formationcondition which is different from that of the oxide semiconductor layer1403 and each have lower resistance.

Next, a source electrode layer 1405 a is formed over the source region1406 a and a drain electrode layer 1405 b is formed over the drainregion 1406 b, so that the thin film transistor 1430 is formed (see FIG.19B). The source electrode layer 1405 a and the drain electrode layer1405 b can be formed in a manner similar to that of the source electrodelayer 405 a and the drain electrode layer 405 b described in Embodiment1, and preferably formed using a heat resistant conductive material. Atthis time, a connection electrode layer 1420 used for a gate wiring tobe formed at the same time.

When the source region 1406 a is provided between the oxidesemiconductor layer 1403 and the source electrode layer 1405 a and thedrain region 1406 b is provided between the oxide semiconductor layer1403 and the drain electrode layer 1405 b, the source electrode layer1405 a and the drain electrode layer 1405 b which are metal layers eachcan be favorably bonded to the oxide semiconductor layer 1403, whichleads to a thermally stable operation as compared to a Schottkyjunction. Moreover, since resistance is reduced, good mobility can beensured even with high drain voltage.

This embodiment is not limited to the structure including the sourceregion 1406 a and the drain region 1406 b; for example, a structure inwhich source and drain regions are not provided may be used.

Next, an oxide insulating film 1407 is formed so as to cover the sourceelectrode layer 1405 a, the drain electrode layer 1405 b, and thechannel protective layer 1418. The oxide insulating film 1407 can beformed to a thickness of at least 1 nm or more using a method by whichimpurities such as water and hydrogen are prevented from being mixed tothe oxide insulating film 1407, such as a CVD method or a sputteringmethod, as appropriate. The oxide insulating film 1407 does not includeimpurities such as moisture, hydrogen ions, and OW and is formed usingan inorganic insulating film which prevents entry of these from theoutside. Specifically, a silicon oxide film, a silicon nitride oxidefilm, an aluminum oxide film, or an aluminum oxynitride film is used.Further, a silicon nitride film or an aluminum nitride film may bestacked so as to be formed over and in contact with the oxide insulatingfilm 1407.

Next, for dehydration or dehydrogenation, heat treatment is performedunder an oxygen gas atmosphere, an inert gas atmosphere (nitrogen,helium, neon, argon, or the like), or under reduced pressure. The heattreatment is performed at a temperature of higher than or equal to 200°C. and lower than or equal to 700° C., preferably, higher than or equalto 350° C. and lower than the strain point of the substrate 1400. Afterthe heat treatment, slow cooling is preferably performed under an oxygenatmosphere. For example, slow cooling may be performed so that thesubstrate temperature is lowered by at least approximately 50° C. to100° C. from the highest heating temperature. In this embodiment, theoxide semiconductor layer 1403 is in a microcrystalline state or in apolycrystalline state. The heat treatment can reduce variation inelectric characteristics of the thin film transistor.

Next, a first contact hole, a second contact hole, a third contact hole,and a fourth contact hole are formed in the oxide insulating film 1407.First, part of the oxide insulating film 1407 is removed by etching,whereby the first contact hole which reaches the source electrode layer1405 a, part of the second contact hole which reaches the gate electrodelayer 1401, and the third contact hole and the fourth contact hole whichreach both end portions of the connection electrode layer 1420 areformed. Further, part of the gate insulating layer 1402 is removed byetching, whereby the second contact hole which reaches the gateelectrode layer 1401 is formed.

Next, a second conductive film is formed over the oxide insulating film1407, and then a source wiring 1425, a first gate wiring 1426, and asecond gate wiring 1427 are formed over the oxide insulating film 1407(see FIG. 19C). The second conductive film is preferably formed using amaterial which is similar to that of the second conductive filmdescribed in Embodiment 1, and a low resistance conductive material suchas aluminum or copper is preferably used. The source wiring 1425overlaps the connection electrode layer 1420 and is formed so as to beconnected to the source electrode layer 1405 a through the first contacthole. The first gate wiring 1426 and the second gate wiring 1427 areformed so as to sandwich the source wiring 1425. Here, the first gatewiring 1426 is formed so as to be connected to the gate electrode layer1401 through the second contact hole and so as to be connected to theconnection electrode layer 1420 through the third contact hole. Thesecond gate wiring 1427 is formed so as to be connected to theconnection electrode layer 1420 through the fourth contact hole.Accordingly, the first gate wiring 1426 and the second gate wiring 1427are electrically connected to each other through the connectionelectrode layer 1420.

Through the above-described steps, the thin film transistor 1430 can beformed.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 7

A semiconductor device and a method for manufacturing the semiconductordevice will be described with reference to FIGS. 20A and 20B. The sameportion as Embodiment 6 or a portion having similar function to thatdescribed in Embodiment 6 and a process can be formed in a mannersimilar to that described in Embodiment 6; therefore, repetitivedescription is omitted.

In a thin film transistor 1431 illustrated in FIG. 20A, a conductivelayer 1409 is provided so as to overlap the gate electrode layer 1401with the channel protective layer 1418 and the oxide insulating film1407 interposed therebetween, and so as to overlap the oxidesemiconductor layer 1403 with the channel protective layer 1418 and theoxide insulating film 1407 interposed therebetween.

FIG. 20A is a cross-sectional view of the thin film transistor 1431included in a semiconductor device. The thin film transistor 1431 is abottom gate thin film transistor and includes the gate electrode layer1401, the gate insulating layer 1402, the oxide semiconductor layer1403, the source region 1406 a, the drain region 1406 b, the sourceelectrode layer 1405 a, the drain electrode layer 1405 b, the oxideinsulating film 1407, the source wiring 1425, and the conductive layer1409 over the substrate 1400 having an insulating surface. Theconductive layer 1409 is provided over the oxide insulating film 1407 sothat the conductive layer 1409 overlaps the gate electrode layer 1401.Although not illustrated in FIG. 20A, a gate wiring and a connectionelectrode layer are also provided in a manner similar to that ofEmbodiment 1.

In a manner similar to that of Embodiment 6, after the oxide insulatingfilm 1407 is formed, heat treatment is performed, so that the oxidesemiconductor layer 1403 which has been subjected to dehydration ordehydrogenation is formed.

In this embodiment, the source region 1406 a and the drain region 1406 bformed over the oxide semiconductor layer are each formed using aZn—O-based microcrystalline film or a Zn—O-based polycrystalline filmand are formed under a film formation condition which is different fromthat of the oxide semiconductor layer 1403 and each are a lowerresistance oxide semiconductor layer than the oxide semiconductor layer1403. Further, the oxide semiconductor layer 1403 is in an amorphousstate.

The conductive layer 1409 can be formed using a material and a methodwhich are similar to those of the source wiring 1425 described inEmbodiment 1. When a pixel electrode layer is provided, the conductivelayer may be formed using a material and a method which are similar tothose of the pixel electrode layer. In this embodiment, a low resistanceconductive material such as aluminum or copper is used for theconductive layer 1409.

The potential of the conductive layer 1409 may be the same as ordifferent from the potential of the gate electrode layer 1401 and canfunction as a second gate electrode layer. Further, the conductive layer1409 may be in a floating state.

In addition, the conductive layer 1409 is provided in a position thatoverlaps the oxide semiconductor layer 1403, whereby in abias-temperature stress test (hereinafter, referred to as a BT test) forexamining reliability of the thin film transistor, the amount of changein threshold voltage of the thin film transistor 1431 between before andafter the BT test can be reduced.

FIG. 20B illustrates an example which is partly different from that inFIG. 20A. The same portion as that described in FIG. 20A or a portionhaving similar function to that illustrated in FIG. 20A and a processcan be formed in a manner similar to that described in FIG. 20A;therefore, repetitive description is omitted.

For example, in a thin film transistor 1432 illustrated in FIG. 20B, theconductive layer 1409 is provided so as to overlap the gate electrodelayer 1401 with the channel protective layer 1418, the oxide insulatingfilm 1407, and an insulating layer 1408 interposed therebetween, and soas to overlap a channel region of the oxide semiconductor layer 1403with the channel protective layer 1418, the oxide insulating film 1407,and the insulating layer 1408 interposed therebetween.

As for the thin film transistor 1432, in a manner similar to that ofEmbodiment 1, after the oxide insulating film 1407 is formed, heattreatment for dehydration or dehydrogenation is performed, and the oxidesemiconductor layer 1403 is formed. The heat treatment is performed at atemperature of higher than or equal to 200° C. and lower than or equalto 700° C., preferably, higher than or equal to 350° C. and lower thanthe strain point of the substrate 1400 under an oxygen gas atmosphere,an inert gas atmosphere (nitrogen, helium, neon, argon, or the like), orunder reduced pressure. Slow cooling is preferably performed under aninert gas atmosphere or an oxygen atmosphere after the heat treatment.Then, a contact hole is formed in the oxide insulating film 1407, andthe source wiring 1425 which is connected to the source electrode layer1405 a is formed.

In FIG. 20B, the insulating layer 1408 which functions as aplanarization film is stacked over the oxide insulating film 1407.

In FIG. 20B, the oxide semiconductor layer 1403 is directly in contactwith the source electrode layer 1405 a and the drain electrode layer1405 b without any source and drain regions.

In the structure illustrated in FIG. 20B, when the conductive layer 1409is provided so as to overlap the oxide semiconductor layer 1403, in a BTtest for examining reliability of the thin film transistor, the amountof change in threshold voltage of the thin film transistor 1432 betweenbefore and after the BT test can be reduced.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 8

In this embodiment, an example of a structure which is partly differentfrom that of Embodiment 1 will be described with reference to FIG. 21.The same portion as Embodiment 1 or a portion having similar function tothat described in Embodiment 1 and a process can be formed in a mannersimilar to that described in Embodiment 1; therefore, repetitivedescription is omitted.

In this embodiment, after a first oxide semiconductor layer is formed, asecond oxide semiconductor film which is used for a source region and adrain region (also referred to as an n⁺ layer or a buffer layer) of athin film transistor is formed over the first oxide semiconductor layer,and then a conductive film is formed.

Next, the first oxide semiconductor layer, the second oxidesemiconductor film, and the conductive film are selectively etched by anetching process, so that the oxide semiconductor layer 403, the sourceregion 404 a, the drain region 404 b, the source electrode layer 405 a,and the drain electrode layer 405 b are formed. Note that part of theoxide semiconductor layer 403 is etched and a groove (depression) isprovided.

Then, a silicon oxide film is formed as the oxide insulating film 407 tobe in contact with the oxide semiconductor layer 403 by a sputteringmethod or a PCVD method. The oxide insulating film 407 which is incontact with the oxide semiconductor layer with reduced resistivity doesnot include impurities such as moisture, hydrogen ions, and OW and isformed using an inorganic insulating film which prevents entry of thesefrom the outside. Specifically, a silicon oxide film, a silicon nitrideoxide film, an aluminum oxide film, or an aluminum oxynitride film isused. Further, a silicon nitride film or an aluminum nitride film may bestacked over the oxide insulating film 407.

In a manner similar to that of Embodiment 1, after the oxide insulatingfilm 407 is formed, heat treatment for dehydration or dehydrogenation isperformed, and the oxide semiconductor layer 403 is formed. The heattreatment is performed at a temperature of higher than or equal to 200°C. and lower than or equal to 700° C., preferably, higher than or equalto 350° C. and lower than the strain point of the substrate 400 under anoxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium, neon,argon, or the like), or under reduced pressure. Slow cooling ispreferably performed under an inert gas atmosphere or an oxygenatmosphere after the heat treatment. The heat treatment allows plasmadamage caused when the oxide insulating film 407 is formed to berepaired. Then, a contact hole is formed in the oxide insulating film407, and the source wiring 425 which is connected to the sourceelectrode layer 405 a is formed. In this manner, a thin film transistor464 can be manufactured (see FIG. 21).

As the source region 404 a and the drain region 404 b in the structureillustrated in FIG. 21, In—Ga—Zn—O-based non-single-crystal is used.Alternatively, an Al—Zn—O-based amorphous film can be used for thesource region 404 a and the drain region 404 b. Further alternatively,an Al—Zn—O-based amorphous film containing nitrogen, that is, anAl—Zn—O—N-based amorphous film (also referred to as an AZON film) may beused for the source region 404 a and the drain region 404 b.

In addition, a source region may be provided between the oxidesemiconductor layer and the source electrode layer, and a drain regionmay be provided between the oxide semiconductor layer 403 and the drainelectrode layer.

The second oxide semiconductor layer used for the source region 404 aand the drain region 404 b of the thin film transistor 464 is preferablythinner than the first oxide semiconductor layer 403 used for a channelformation region and preferably has higher conductivity (electricalconductivity) than the first oxide semiconductor layer 403.

Further, the first oxide semiconductor layer 403 used for the channelformation region has an amorphous structure and the second oxidesemiconductor layer used for the source region and the drain regionincludes a crystal grain (nanocrystal) in an amorphous structure in somecases. The crystal grain (nanocrystal) in the second oxide semiconductorlayer used for the source region and the drain region has a diameter of1 nm to 10 nm, typically, approximately 2 nm to 4 nm.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 9

In this embodiment, an example will be described below in which at leastpart of a driver circuit and a thin film transistor to be disposed in apixel portion are formed over one substrate.

The thin film transistor provided in the pixel portion is formedaccording to any of Embodiments 1 to 8. Further, the thin filmtransistor described in any of Embodiments 1 to 8 is an n-channel TFT.Thus, part of a driver circuit that can be formed using n-channel TFTsamong driver circuits is formed over the same substrate as that for thethin film transistor in the pixel portion.

FIG. 22A illustrates an example of a block diagram of an active matrixdisplay device, which is one example of the display device. A pixelportion 5301, a first scan line driver circuit 5302, a second scan linedriver circuit 5303, and a signal line driver circuit 5304 are providedover a substrate 5300 of a display device. In the pixel portion 5301, aplurality of signal lines extending from the signal line driver circuit5304 are provided, and a plurality of scan lines extending from thefirst scan line driver circuit 5302 and the second scan line drivercircuit 5303 are provided. Note that in cross regions of the scan linesand the signal lines, pixels each having a display element are arrangedin a matrix. Further, the substrate 5300 of the display device isconnected to a timing control circuit 5305 (also referred to as acontroller or a control IC) through a connection portion of a flexibleprinted circuit (FPC) or the like.

In FIG. 22A, the first scan line driver circuit 5302, the second scanline driver circuit 5303, and the signal line driver circuit 5304 areformed over the same substrate 5300 as the pixel portion 5301.Accordingly, the number of parts such as driver circuits providedoutside is reduced, so that cost can decrease. Further, a connectionportion used for extending a wiring when a driver circuit is providedoutside the substrate 5300 has a smaller number of connections, so thatreliability and yield can be improved.

Note that the timing control circuit 5305 supplies a start signal forthe first scan line driver circuit (GSP1) and a clock signal for thescan line driver circuit (GCK1) to the first scan line driver circuit5302, as an example. In addition, the timing control circuit 5305supplies, for example, a start signal for the second scan line drivercircuit (GSP2) (also referred to as a start pulse) and a clock signalfor the scan line driver circuit (GCK2) to the second scan line drivercircuit 5303. A start signal for the signal line driver circuit (SSP), aclock signal for the signal line driver circuit (SCK), data for a videosignal (DATA) (also simply referred to as a video signal), and a latchsignal (LAT) are supplied to the signal line driver circuit 5304. Notethat each clock signal may be a plurality of clock signals withdifferent phases, or may be supplied with an inverted clock signal(CKB). Note that either the first scan line driver circuit 5302 or thesecond scan line driver circuit 5303 can be omitted.

In FIG. 22B, a circuit with a low drive frequency (e.g., the first scanline driver circuit 5302 and the second scan line driver circuit 5303)is formed over the same substrate 5300 as the pixel portion 5301, andthe signal line driver circuit 5304 is formed over another substratewhich is different from the substrate provided with the pixel portion5301. This structure enables a driver circuit formed over the substrate5300 using a thin film transistor having low field effect mobility,compared with a transistor formed using a single crystal semiconductor.Accordingly, increase in the size of the display device, reduction inthe number of steps, reduction in cost, improvement in yield, or thelike can be achieved.

The thin film transistors described in Embodiments 1 to 8 are n-channelTFTs. In FIGS. 23A and 23B, an example of a structure and operation of asignal line driver circuit formed using an n-channel TFT is described.

The signal line driver circuit includes a shift register 5601 and aswitching circuit 5602. The switching circuit 5602 includes a pluralityof switching circuits 5602_1 to 5602_N (N is a natural number). Theswitching circuits 5602_1 to 5602_N each include a plurality of thinfilm transistors 5603_1 to 5603_k (k is a natural number). An example inwhich the thin film transistors 5603_1 to 5603_k are n-channel TFTs isdescribed.

A connection relation of the signal line driver circuit will bedescribed by using the switching circuit 5602_1 as an example. Firstterminals of the thin film transistors 5603_1 to 5603_k are connected towirings 5604_1 to 5604_k, respectively. Second terminals of the thinfilm transistors 5603_1 to 5603_k are connected to signal wirings S1 toSk, respectively. Gates of the thin film transistors 5603_1 to 5603_kare connected to a wiring 5605_1.

The shift register 5601 has a function of sequentially outputting Hlevel signals (also referred to as an H signal or a high power supplypotential level) to the wirings 5605_1 to 5605_N, and a function ofsequentially selecting the switching circuits 5602_1 to 5602_N.

The switching circuit 5602_1 has a function of controlling conductionstates between the wirings 5604_1 to 5604_k and the signal lines S1 toSk (conduction between the first terminal and the second terminal), thatis, a function of controlling whether the potentials of the wirings5604_1 to 5604_k are supplied or not to the signal lines S1 to Sk. Inthis manner, the switching circuit 5602_1 has a function of a selector.The thin film transistors 5603_1 to 5603_k have functions of controllingconduction states between the wiring 5604_1 to 5604_k and the signallines S1 to Sk, that is, functions of supplying potentials of thewirings 5604_1 to 5604_k to the signal lines S1 to Sk, respectively. Inthis manner, each of the thin film transistors 5603_1 to 5603_kfunctions as a switch.

Note that the data for a video signal (DATA) is input to the wirings5604_1 to 5604_k. The data for a video signal (DATA) is an analog signalcorresponding to image data or an image signal in many cases.

Next, operation of the signal line driver circuit illustrated in FIG.23A is described with reference to a timing chart in FIG. 23B. In FIG.23B, an example of signals Sout_1 to Sout_N and signals Vdata_1 toVdata_k is illustrated. The signals Sout_1 to Sout_N are examples ofoutput signals of the shift register 5601, and the signals Vdata_1 toVdata_k are examples of signals which are input to the wirings 5604_1 to5604_k, respectively. Note that one operation period of the signal linedriver circuit corresponds to one gate selection period in a displaydevice. For example, one gate selection period is divided into periodsT1 to TN. The periods T1 to TN are periods for writing the data for avideo signal (DATA) to pixels in a selected TOW.

In the periods T1 to TN, the shift register 5601 sequentially outputs Hlevel signals to the wirings 5605_1 to 5605_N. For example, in theperiod T1, the shift register 5601 outputs a high level signal to thewiring 5605_1. Then, the thin film transistors 5603_1 to 5603_k areturned on, so that the wirings 5604_1 to 5604_k and the signal lines S1to Sk are brought into conduction. In this case, Data (S1) to Data (Sk)are input to the wirings 5604_1 to 5604_k, respectively. The Data (S1)to Data (Sk) are input to pixels in a selected row in a first to k-thcolumns through the thin film transistors 5603_1 to 5603_k,respectively. Thus, in the periods T1 to TN, the data for a video signal(DATA) is sequentially written to the pixels in the selected row by kcolumns.

By writing the data for a video signal (DATA) to pixels by a pluralityof columns, the number of the data for a video signal (DATA) or thenumber of wirings can be reduced. Accordingly, the number of connectionsto external circuits can be reduced. Further, by writing the data for avideo signal (DATA) to pixels of a plurality of columns each time, writetime can be extended, and shortage of writing of the data for a videosignal (DATA) can be prevented.

Note that for the shift register 5601 and the switching circuit 5602, acircuit formed using the thin film transistor described in Embodiments 1to 8 can be used. In that case, all the transistors included in theshift register 5601 can be only n-channel transistors or only p-channeltransistors.

One mode of a shift register which is used for part of a scan linedriver circuit and/or a signal line driver circuit will be describedwith reference to FIGS. 24A to 24C and FIGS. 25A and 25B.

The scan line driver circuit includes a shift register. Additionally,the scan line driver circuit may include a level shifter, a buffer, orthe like in some cases. In the scan line driver circuit, when the clocksignal (CK) and the start pulse signal (SP) are input to the shiftregister, a selection signal is generated. The generated selectionsignal is buffered and amplified by the buffer, and the resulting signalis supplied to a corresponding scan line. Gate electrodes of transistorsin pixels of one line are connected to the scan line. Since thetransistors in the pixels of one line have to be turned on all at once,a buffer which can feed a large amount of current is used.

The shift register includes first to N-th pulse output circuits 10_1 to10_N (N is a natural number of greater than or equal to 3) (see FIG.24A). A first clock signal CK1 from a first wiring 11, a second clocksignal CK2 from a second wiring 12, a third clock signal CK3 from athird wiring 13, and a fourth clock signal CK4 from a fourth wiring 14are supplied to the first to N-th pulse output circuits 10_1 to 10_N inthe shift register illustrated in FIG. 24A. A start pulse SP1 (firststart pulse) from a fifth wiring 15 is input to the first pulse outputcircuit 10_1. A signal from a pulse output circuit of the previous stage(also referred to as a previous stage signal OUT (n−1) (n is a naturalnumber of greater than or equal to 2) is input to the n-th pulse outputcircuit 10_n (n is a natural number of greater than or equal to 2 andless than or equal to N) of the second and subsequent stages. A signalfrom the third pulse output circuit 10_3 which is two stages after thefirst pulse output circuit 10_1 is input to the first pulse outputcircuit 10_1, or a signal from the (n+2)-th pulse output circuit10_(n+2) which is two stages after the n-th pulse output circuit 10_n isinput to the n-th pulse output circuit 10_n of the second and subsequentstages (also referred to as a subsequent stage signal OUT (n+2)). Fromthe pulse output circuit of each stage, a first output signal OUT (1)(SR) to be input to a pulse output circuit of a previous stage and/or apulse output circuit of a subsequent stage and a second output signalOUT (1) which is input to another wiring or the like are output. Notethat as illustrated in FIG. 24A, a subsequent stage signal OUT (n+2) isnot input to the last two stages of the shift register; therefore, as anexample, a second start pulse SP2 and a third start pulse SP3 may beinput thereto, respectively.

Note that a clock signal (CK) is a signal which alternates between an Hlevel signal and an L level signal (also referred to as an L signal or alow power supply potential level) at a regular interval. Here, the firstto fourth clock signals (CK1) to (CK4) are sequentially delayed by aquarter of a cycle. In this embodiment, by using the first to fourthclock signals (CK1) to (CK4), control or the like of driving of a pulseoutput circuit is performed. Although the clock signal is used as a GCKor an SCK in accordance with a driver circuit to which the clock signalis input, the clock signal is described as a CK here.

A first input terminal 21, a second input terminal 22, and a third inputterminal 23 are electrically connected to any of the first to fourthwirings 11 to 14. For example, in FIG. 24A, the first input terminal 21of the first pulse output circuit 10_1 is electrically connected to thefirst wiring 11, the second input terminal 22 of the first pulse outputcircuit 10_1 is electrically connected to the second wiring 12, and thethird input terminal 23 of the first pulse output circuit 10_1 iselectrically connected to the third wiring 13. In addition, the firstinput terminal 21 of the second pulse output circuit 10_2 iselectrically connected to the second wiring 12, the second inputterminal 22 of the second pulse output circuit 10_2 is electricallyconnected to the third wiring 13, and the third input terminal 23 of thesecond pulse output circuit 102 is electrically connected to the fourthwiring 14.

Each of the first to N-th pulse output circuits 10_1 to 10_N includesthe first input terminal 21, the second input terminal 22, the thirdinput terminal 23, a fourth input terminal 24, a fifth input terminal25, a first output terminal 26, and a second output terminal 27 (seeFIG. 24B). In the first pulse output circuit 10_1, the first clocksignal CK1 is input to the first input terminal 21, the second clocksignal CK2 is input to the second input terminal 22, the third clocksignal CK3 is input to the third input terminal 23, the start pulse isinput to the fourth input terminal 24, a subsequent stage signal OUT (3)is input to the fifth input terminal 25, a first output signal OUT (1)(SR) is output from the first output terminal 26, and a second outputsignal OUT (1) is output from the second output terminal 27.

Next, an example of a specific circuit structure of the pulse outputcircuit illustrated in FIG. 24B will be described with reference to FIG.24C.

The pulse output circuit illustrated in FIG. 24C includes first tothirteenth transistors 31 to 43. In addition to the first to fifth inputterminals 21 to 25, the first output terminal 26, and the second outputterminal 27, signals or power supply potentials are supplied to thefirst to thirteenth transistors 31 to 43 from a power supply line 51 towhich a first high power supply potential VDD is supplied, a powersupply line 52 to which a second high power supply potential VCC issupplied, and a power supply line 53 to which a low power supplypotential VSS is supplied. Here, the magnitude relation among powersupply potentials of the power supply lines illustrated in FIG. 24C isset as follows: the first power supply potential VDD is higher than orequal to the second power supply potential VCC, and the second powersupply potential VCC is higher than the third power supply potentialVSS. Although the first to fourth clock signals (CK1) to (CK4) aresignals which alternate between an H level signal and an L level signalat a regular interval, a potential is VDD when the clock signal is at anH level, and a potential is VSS when the clock signal is at an L level.Note that the potential VDD of the power supply line 51 is higher thanthe potential VCC of the power supply line 52, so that there is noeffect on an operation, the potential applied to a gate electrode of atransistor can be low, a shift of the threshold voltage of thetransistor can be reduced, and deterioration can be suppressed.

In FIG. 24C, a first terminal of the first transistor 31 is electricallyconnected to the power supply line 51, a second terminal of the firsttransistor 31 is electrically connected to a first terminal of the ninthtransistor 39, and a gate electrode of the first transistor 31 iselectrically connected to the fourth input terminal 24. A first terminalof the second transistor 32 is electrically connected to the powersupply line 53, a second terminal of the second transistor 32 iselectrically connected to the first terminal of the ninth transistor 39,and a gate electrode of the second transistor 32 is electricallyconnected to a gate electrode of the fourth transistor 34. A firstterminal of the third transistor 33 is electrically connected to thefirst input terminal 21, and a second terminal of the third transistor33 is electrically connected to the first output terminal 26. A firstterminal of the fourth transistor 34 is electrically connected to thepower supply line 53, and a second terminal of the fourth transistor 34is electrically connected to the first output terminal 26. A firstterminal of the fifth transistor 35 is electrically connected to thepower supply line 53, a second terminal of the fifth transistor 35 iselectrically connected to the gate electrode of the second transistor 32and the gate electrode of the fourth transistor 34, and a gate electrodeof the fifth transistor 35 is electrically connected to the fourth inputterminal 24. A first terminal of the sixth transistor 36 is electricallyconnected to the power supply line 52, a second terminal of the sixthtransistor 36 is electrically connected to the gate electrode of thesecond transistor 32 and the gate electrode of the fourth transistor 34,and a gate electrode of the sixth transistor 36 is electricallyconnected to the fifth input terminal 25. A first terminal of theseventh transistor 37 is electrically connected to the power supply line52, a second terminal of the seventh transistor 37 is electricallyconnected to a second terminal of the eighth transistor 38, and a gateelectrode of the seventh transistor 37 is electrically connected to thethird input terminal 23. A first terminal of the eighth transistor 38 iselectrically connected to the gate electrode of the second transistor 32and the gate electrode of the fourth transistor 34, and a gate electrodeof the eighth transistor 38 is electrically connected to the secondinput terminal 22. A first terminal of the ninth transistor 39 iselectrically connected to the second terminal of the first transistor 31and the second terminal of the second transistor 32, a second terminalof the ninth transistor 39 is electrically connected to the gateelectrode of the third transistor 33 and a gate electrode of the tenthtransistor 40, and a gate electrode of the ninth transistor 39 iselectrically connected to the power supply line 51. A first terminal ofthe tenth transistor 40 is electrically connected to the first inputterminal 21, a second terminal of the tenth transistor 40 iselectrically connected to the second output terminal 27, and a gateelectrode of the tenth transistor 40 is electrically connected to thesecond terminal of the ninth transistor 39. A first terminal of theeleventh transistor 41 is electrically connected to the power supplyline 53, a second terminal of the eleventh transistor 41 is electricallyconnected to the second output terminal 27, and a gate electrode of theeleventh transistor 41 is electrically connected to the gate electrodeof the second transistor 32 and the gate electrode of the fourthtransistor 34. A first terminal of the twelfth transistor 42 iselectrically connected to the power supply line 53, a second terminal ofthe twelfth transistor 42 is electrically connected to the second outputterminal 27, and a gate electrode of the twelfth transistor 42 iselectrically connected to the gate electrode of the seventh transistor37. A first terminal of the thirteenth transistor 43 is electricallyconnected to the power supply line 53, a second terminal of thethirteenth transistor 43 is electrically connected to the first outputterminal 26, and a gate electrode of the thirteenth transistor 43 iselectrically connected to the gate electrode of the seventh transistor37.

In FIG. 24C, a connection portion of the gate electrode of the thirdtransistor 33, the gate electrode of the tenth transistor 40, and thesecond terminal of the ninth transistor 39 is a node A. A connectionportion of the gate electrode of the second transistor 32, the gateelectrode of the fourth transistor 34, the second terminal of the fifthtransistor 35, the second terminal of the sixth transistor 36, the firstterminal of the eighth transistor 38, and the gate electrode of theeleventh transistor 41 is a node B.

In FIG. 25A, signals which are input or output to/from the first to thefifth input terminals 21 to 25, the first output terminal 26, and thesecond output terminal 27 when the pulse output circuit illustrated inFIG. 24C is applied to the first pulse output circuit 10_1 areillustrated.

Specifically, the first clock signal CK1 is input to the first inputterminal 21, the second clock signal CK2 is input to the second inputterminal 22, the third clock signal CK3 is input to the third inputterminal 23, the start pulse is input to the fourth input terminal 24,the subsequent stage signal OUT (3) is input to the fifth input terminal25, the first output signal OUT (1) (SR) is output from the first outputterminal 26, and the second output signal OUT (1) is output from thesecond output terminal 27.

Note that a thin film transistor is an element having at least threeterminals of a gate, a drain, and a source. The thin film transistorincludes a semiconductor whose channel region is formed at a region thatoverlaps the gate, and the potential of the gate is controlled, wherebycurrent which flows between the drain and the source through the channelregion can be controlled. Here, since the source and the drain of thethin film transistor may interchange depending on the structure, theoperating condition, and the like of the thin film transistor, it isdifficult to define which is a source or a drain. Therefore, a regionfunctioning as a source and a drain is not called the source or thedrain in some cases. In such a case, for example, one of the source andthe drain may be referred to as a first terminal and the other thereofmay be referred to as a second terminal.

Note that in FIGS. 24C and 25A, a capacitor may be provided in order toperform bootstrap operation effected by the node A in a floating state.A capacitor whose one electrode is electrically connected to the node Bmay be provided in order to hold the potential of the node B.

Here, a timing chart of a shift register in which a plurality of pulseoutput circuits illustrated in FIG. 25A are provided is illustrated inFIG. 25B. Note that in FIG. 25B, when the shift register is a scan linedriver circuit, a period 61 is a vertical retrace period and a period 62is a gate selection period.

Note that as illustrated in FIG. 25A, when the ninth transistor 39having the gate to which the second power supply potential VCC isapplied is provided, there are the following advantages before or afterthe bootstrap operation.

Without the ninth transistor 39 whose gate electrode is supplied withthe second power supply potential VCC, when a potential of the node A israised by bootstrap operation, a potential of a source which is thesecond terminal of the first transistor 31 increases to a value higherthan the first power supply potential VDD. Then, the source of the firsttransistor 31 is switched to the first terminal side, that is, the powersupply line 51 side. Therefore, in the first transistor 31, a largeamount of bias voltage is applied and thus great stress is appliedbetween a gate and a source and between the gate and a drain, which cancause deterioration in the transistor. When the ninth transistor 39 isprovided whose gate electrode is supplied with the second power supplypotential VCC, a potential of the node A is raised by bootstrapoperation, but at the same time, an increase in a potential of thesecond terminal of the first transistor 31 can be prevented. In otherwords, with the ninth transistor 39, negative bias voltage appliedbetween a gate and a source of the first transistor 31 can be reduced.Accordingly, with a circuit structure in this embodiment, negative biasvoltage applied between a gate and a source of the first transistor 31can be reduced, so that deterioration in the first transistor 31, whichis due to stress, can further be restrained.

Note that the ninth transistor 39 may be provided in any places wherethe ninth transistor 39 is connected between the second terminal of thefirst transistor 31 and the gate of the third transistor 33 through thefirst terminal and the second terminal. When a shift register includes aplurality of pulse output circuits in this embodiment, the ninthtransistor 39 may be omitted in a signal line driver circuit which has alarger number of stages than a scan line driver circuit, and there is anadvantage of decreasing the number of transistors.

Note that when oxide semiconductors are used for semiconductor layersfor the first to the thirteenth transistors 31 to 43, the off current ofthe thin film transistors can be reduced, the on current and the fieldeffect mobility can be increased, and the degree of deterioration can bereduced, whereby malfunction in a circuit can decrease. Compared with atransistor formed using an oxide semiconductor and a transistor formedusing amorphous silicon, the degree of deterioration of the transistordue to the application of a high potential to the gate electrode is low.Therefore, similar operation can be obtained even when the first powersupply potential VDD is supplied to the power supply line which suppliesthe second power supply potential VCC, and the number of power supplylines which are led between circuits can decrease; therefore, the sizeof the circuit can be reduced

Note that the clock signal which is supplied from the third inputterminal 23 to the gate electrode of the seventh transistor 37 and theclock signal which is supplied from the second input terminal 22 to thegate electrode of the eighth transistor 38 are the same as the clocksignal supplied from the second input terminal 22 to the gate electrodeof the seventh transistor 37 and the clock signal supplied from thethird input terminal 23 to the gate electrode of the eighth transistor38, respectively. Thus, these signals function in a manner similar torespective signals even when connections are replaced. Note that in theshift register illustrated in FIG. 25A, the state is changed from thestate where both the seventh transistor 37 and the eighth transistor 38are in an on state, to the state where the seventh transistor 37 isturned off and the eighth transistor 38 is in an on state, and then tothe state where both the seventh transistor 37 and the eighth transistor38 are turned off. Accordingly, the decrease in the potential of thenode B is caused twice, which is due to the decrease in the potentialapplied to the gate electrode of the seventh transistor 37 by thedecrease in the potential of the third input terminal 23 and thedecrease in the potential applied to the gate electrode of the eighthtransistor 38 by the decrease in the potential of the second inputterminal 22. On the other hand, when the shift register illustrated inFIG. 25A is operated in accordance with a period illustrated in FIG.25B, the state is changed from the state where both the seventhtransistor 37 and the eighth transistor 38 are in an on state to thestate where the seventh transistor 37 is in an on state and the eighthtransistor 38 is turned off, and then to the state where both theseventh transistor 37 and the eighth transistor 38 are turned off.Accordingly, the number of times of the decrease in the potential of thenode B, which is due to the decrease in the potential of the secondinput terminal 22 and the potential of the third input terminal 23, canbe reduced to one because of the decrease in the potential of the gateelectrode of the eighth transistor 38. Therefore, the connectionrelation, that is, the clock signal CK3 is supplied from the third inputterminal 23 to the gate electrode of the seventh transistor 37 and theclock signal CK2 is supplied from the second input terminal 22 to thegate electrode of the eighth transistor 38, is preferable. That isbecause the number of times of the change in the potential of the node Bcan be reduced, whereby the noise can be decreased.

In this way, in a period during which the potential of the first outputterminal 26 and the potential of the second output terminal 27 are eachheld at an L level, an H level signal is regularly supplied to the nodeB; therefore, malfunction of the pulse output circuit can be suppressed.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 10

A thin film transistor is manufactured, and a semiconductor devicehaving a display function (also referred to as a display device) can bemanufactured using the thin film transistor in a pixel portion andfurther in a driver circuit. Further, part or whole of the drivercircuit can be formed over the same substrate as the pixel portion,using the thin film transistor, whereby a system-on-panel can beobtained.

The display device includes a display element. As the display element, aliquid crystal element (also referred to as a liquid crystal displayelement) or a light-emitting element (also referred to as alight-emitting display element) can be used. The light-emitting elementincludes, in its category, an element whose luminance is controlled bycurrent or voltage, and specifically includes, in its category, aninorganic electroluminescent (EL) element, an organic EL element, andthe like. Furthermore, a display medium whose contrast is changed by anelectric effect, such as electronic ink, can be used.

In addition, the display device includes a panel in which a displayelement is sealed, and a module in which an IC and the like including acontroller are mounted on the panel. Furthermore, an element substrate,which corresponds to an embodiment before the display element iscompleted in a manufacturing process of the display device, is providedwith a means for supplying current to the display element in each of aplurality of pixels. The element substrate may be specifically in astate where only a pixel electrode of a display element is formed or ina state after a conductive film to be a pixel electrode is formed andbefore the conductive film is etched to form a pixel electrode, and canhave any mode.

Note that a display device in this specification means an image displaydevice, a display device, or a light source (including a lightingdevice). Further, the display device includes the following modules inits category: a module including a connector such as a flexible printedcircuit (FPC), a tape automated bonding (TAB) tape, or a tape carrierpackage (TCP) attached; a module having a TAB tape or a TCP which isprovided with a printed wiring board at the end thereof; and a modulehaving an integrated circuit (IC) which is directly mounted on a displayelement by a chip on glass (COG) method.

The appearance and a cross section of a liquid crystal display panel,which is an embodiment of a semiconductor device, will be described withreference to FIGS. 26A to 26C. FIGS. 26A and 26B are each a plan view ofa panel in which highly reliable thin film transistors 4010 and 4011each including the oxide semiconductor layer described in any ofEmbodiments 1 to 8, and a liquid crystal element 4013 are sealed betweena first substrate 4001 and a second substrate 4006 with a sealant 4005.FIG. 26C is a cross-sectional view taken along line M-N of FIGS. 26A and26B.

The sealant 4005 is provided so as to surround a pixel portion 4002 anda scan line driver circuit 4004 which are provided over the firstsubstrate 4001. The second substrate 4006 is provided over the pixelportion 4002 and the scan line driver circuit 4004. Therefore, the pixelportion 4002 and the scan line driver circuit 4004 are sealed togetherwith a liquid crystal layer 4008, by the first substrate 4001, thesealant 4005, and the second substrate 4006. A signal line drivercircuit 4003 that is formed using a single crystal semiconductor film ora polycrystalline semiconductor film over a substrate separatelyprepared is mounted in a region that is different from the regionsurrounded by the sealant 4005 over the first substrate 4001.

Note that there is no particular limitation on the connection method ofa driver circuit which is separately formed, and a COG method, a wirebonding method, a TAB method, or the like can be used. FIG. 26Aillustrates an example in which the signal line driver circuit 4003 ismounted by a COG method and FIG. 26B illustrates an example in which thesignal line driver circuit 4003 is mounted by a TAB method.

Each of the pixel portion 4002 and the scan line driver circuit 4004which are provided over the first substrate 4001 includes a plurality ofthin film transistors. FIG. 26C illustrates the thin film transistor4010 included in the pixel portion 4002 and the thin film transistor4011 included in the scan line driver circuit 4004. Over the thin filmtransistors 4010 and 4011, insulating layers 4020 and 4021 are provided.

Any of the highly reliable thin film transistors including the oxidesemiconductor layer which is described in any of Embodiments 1 to 8 canbe used as the thin film transistors 4010 and 4011. In this embodiment,the thin film transistors 4010 and 4011 are n-channel thin filmtransistors.

A pixel electrode layer 4030 included in the liquid crystal element 4013is electrically connected to the thin film transistor 4010. A counterelectrode layer 4031 of the liquid crystal element 4013 is provided forthe second substrate 4006. A portion where the pixel electrode layer4030, the counter electrode layer 4031, and the liquid crystal layer4008 overlap one another corresponds to the liquid crystal element 4013.Note that the pixel electrode layer 4030 and the counter electrode layer4031 are provided with an insulating layer 4032 and an insulating layer4033 respectively which each function as an alignment film, and theliquid crystal layer 4008 is sandwiched between the pixel electrodelayer 4030 and the counter electrode layer 4031 with the insulatinglayers 4032 and 4033 interposed therebetween.

Note that the first substrate 4001 and the second substrate 4006 can beformed using glass, metal (typically, stainless steel), ceramic, orplastic. As plastic, a fiberglass-reinforced plastics (FRP) plate, apolyvinyl fluoride (PVF) film, a polyester film, or an acrylic resinfilm can be used. In addition, a sheet with a structure in which analuminum foil is sandwiched between PVF films or polyester films can beused.

A spacer 4035 is a columnar spacer obtained by selective etching of aninsulating film and is provided in order to control the distance (a cellgap) between the pixel electrode layer 4030 and the counter electrodelayer 4031. Alternatively, a spherical spacer may also be used. Inaddition, the counter electrode layer 4031 is electrically connected toa common potential line formed over the same substrate as the thin filmtransistor 4010. With the use of a common connection portion, thecounter electrode layer 4031 and the common potential line can beelectrically connected to each other by conductive particles arrangedbetween a pair of substrates. Note that the conductive particles areincluded in the sealant 4005.

Alternatively, liquid crystal exhibiting a blue phase for which analignment film is unnecessary may be used. A blue phase is one of liquidcrystal phases, which is generated just before a cholesteric phasechanges into an isotropic phase while temperature of cholesteric liquidcrystal is increased. Since the blue phase is generated within an onlynarrow range of temperature, a liquid crystal composition containing achiral agent at 5 wt % or more so as to improve the temperature range isused for the liquid crystal layer 4008. The liquid crystal compositionwhich includes a liquid crystal exhibiting a blue phase and a chiralagent has a short response time of 1 msec or less, has optical isotropy,which makes the alignment process unneeded, and has a small viewingangle dependence.

An embodiment of the present invention can also be applied to areflective liquid crystal display device or a semi-transmissive liquidcrystal display device, in addition to a transmissive liquid crystaldisplay device.

An example of the liquid crystal display device is described in which apolarizing plate is provided on the outer surface of the substrate (onthe viewer side) and a coloring layer (color filter) and an electrodelayer used for a display element are provided on the inner surface ofthe substrate; however, the polarizing plate may be provided on theinner surface of the substrate. The stacked structure of the polarizingplate and the coloring layer is not limited to this embodiment and maybe set as appropriate depending on materials of the polarizing plate andthe coloring layer or conditions of manufacturing process. Further, alight-blocking film serving as a black matrix may be provided.

In order to reduce surface unevenness of the thin film transistor and toimprove reliability of the thin film transistor, the thin filmtransistor obtained in any of the above embodiments is covered with theinsulating layers (the insulating layer 4020 and the insulating layer4021) serving as a protective film or a planarizing insulating film.Note that the protective film is provided to prevent entry ofcontaminant impurities such as organic substance, metal, or moistureexisting in air and is preferably a dense film. The protective film maybe formed with a single layer or a stacked layer of a silicon oxidefilm, a silicon nitride film, a silicon oxynitride film, a siliconnitride oxide film, an aluminum oxide film, an aluminum nitride film, analuminum oxynitride film, and/or an aluminum nitride oxide film by asputtering method. Although an example in which the protective film isformed by a sputtering method is described in this embodiment, anembodiment of the present invention is not limited to this method and avariety of methods may be employed.

In this embodiment, the insulating layer 4020 having a stacked-layerstructure is formed as a protective film. Here, as a first layer of theinsulating layer 4020, a silicon oxide film is formed by a sputteringmethod. The use of a silicon oxide film as a protective film has aneffect of preventing hillock of an aluminum film used for the source anddrain electrode layers.

As a second layer of the protective film, an insulating layer is formed.Here, as a second layer of the insulating layer 4020, a silicon nitridefilm is formed by a sputtering method. The use of the silicon nitridefilm as the protective film can prevent mobile ions such as sodium ionsfrom entering a semiconductor region, thereby suppressing variations inelectric properties of the TFT.

Further, heat treatment (at 300° C. or lower) may be performed under anitrogen atmosphere or an air atmosphere after the formation of theprotective film.

The insulating layer 4021 is formed as the planarizing insulating film.As the insulating layer 4021, an organic material having heat resistancesuch as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can beused. Other than such organic materials, it is also possible to use alow-dielectric constant material (a low-k material), a siloxane-basedresin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), orthe like. Note that the insulating layer 4021 may be formed by stackinga plurality of insulating films formed of these materials.

Note that the siloxane-based resin corresponds to a resin including aSi—O—Si bond formed using a siloxane-based material as a startingmaterial. The siloxane-based resin may include as a substituent anorganic group (e.g., an alkyl group or an aryl group) or a fluoro group.In addition, the organic group may include a fluoro group.

There is no particular limitation on the formation method of theinsulating layer 4021, and the following method can be employeddepending on the material: a sputtering method, an SOG method, a spincoating method, a dipping method, a spray coating method, a dropletdischarge method (e.g., an ink-jet method, screen printing, offsetprinting, or the like), a doctor knife, a roll coater, a curtain coater,a knife coater, or the like. The baking step of the insulating layer4021 also serves as annealing of the semiconductor layer, whereby asemiconductor device can be manufactured efficiently.

The pixel electrode layer 4030 and the counter electrode layer 4031 canbe formed using a light-transmitting conductive material such as indiumoxide containing tungsten oxide, indium zinc oxide containing tungstenoxide, indium oxide containing titanium oxide, indium tin oxidecontaining titanium oxide, indium tin oxide (hereinafter referred to asITO), indium zinc oxide, indium tin oxide to which silicon oxide isadded, or the like.

Conductive compositions including a conductive high molecule (alsoreferred to as a conductive polymer) can be used for the pixel electrodelayer 4030 and the counter electrode layer 4031. The pixel electrodeformed using the conductive composition preferably has a sheetresistance of less than or equal to 10000 ohms per square and a lighttransmittance of greater than or equal to 70% at a wavelength of 550 nm.Further, the resistivity of the conductive high molecule included in theconductive composition is preferably less than or equal to 0.1 Ω·cm.

As the conductive high molecule, a so-called π-electron conjugatedconductive polymer can be used. For example, polyaniline or a derivativethereof, polypyrrole or a derivative thereof, polythiophene or aderivative thereof, a copolymer of two or more kinds of them, and thelike can be given.

Further, a variety of signals and potentials are supplied to the signalline driver circuit 4003 which is formed separately, the scan linedriver circuit 4004, or the pixel portion 4002 from an FPC 4018.

A connection terminal electrode 4015 is formed using the same conductivefilm as the pixel electrode layer 4030 included in the liquid crystalelement 4013. A terminal electrode 4016 is formed using the sameconductive film as the source and drain electrode layers included in thethin film transistor 4011.

The connection terminal electrode 4015 is electrically connected to aterminal included in the FPC 4018 via an anisotropic conductive film4019.

FIGS. 26A to 26C illustrate an example in which the signal line drivercircuit 4003 is formed separately and mounted on the first substrate4001; however, an embodiment of the present invention is not limited tothis structure. The scan line driver circuit may be separately formedand then mounted, or only part of the signal line driver circuit or partof the scan line driver circuit may be separately formed and thenmounted.

FIG. 27 illustrates an example in which a liquid crystal display moduleis formed as a semiconductor device using a TFT substrate 2600 which ismanufactured according to the manufacturing method disclosed in thisspecification.

FIG. 27 illustrates an example of a liquid crystal display module, inwhich the TFT substrate 2600 and a counter substrate 2601 are fixed toeach other with a sealant 2602, and a pixel portion 2603 including a TFTor the like, a display element 2604 including a liquid crystal layer,and a coloring layer 2605, are provided between the substrates to form adisplay region. The coloring layer 2605 is necessary to perform colordisplay. In the RGB system, respective coloring layers corresponding tocolors of red, green, and blue are provided for respective pixels. Apolarizing plate 2606 is provided on the outer side of the countersubstrate 2601, while a polarizing plate 2607 and a diffusion plate 2613are provided on the outer side of the TFT substrate 2600. A light sourceincludes a cold cathode tube 2610 and a reflective plate 2611, and acircuit substrate 2612 is connected to a wiring circuit portion 2608 ofthe TFT substrate 2600 by a flexible wiring board 2609 and includes anexternal circuit such as a control circuit or a power supply circuit.The polarizing plate and the liquid crystal layer may be stacked with aretardation plate interposed therebetween.

The liquid crystal display module can employ a TN (Twisted Nematic)mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching)mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (PatternedVertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell)mode, an OCB (Optical Compensated Birefringence) mode, an FLC(Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric LiquidCrystal) mode, or the like.

Through this process, a highly reliable liquid crystal display panel asa semiconductor device can be manufactured.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 11

An example of electronic paper will be described as a semiconductordevice.

The semiconductor device can be used for electronic paper in whichelectronic ink is driven by an element electrically connected to aswitching element. The electronic paper is also referred to as anelectrophoretic display device (an electrophoretic display) and isadvantageous in that it has the same level of readability as plainpaper, it has lower power consumption than other display devices, and itcan be made thin and lightweight.

Electrophoretic displays can have various modes. Electrophoreticdisplays contain a plurality of microcapsules dispersed in a solvent ora solute, each microcapsule containing first particles which arepositively charged and second particles which are negatively charged. Byapplying an electric field to the microcapsules, the particles in themicrocapsules move in opposite directions to each other and only thecolor of the particles gathering on one side is displayed. Note that thefirst particles and the second particles each contain dye and do notmove without an electric field. Moreover, the first particles and thesecond particles have different colors (which may be colorless).

Thus, an electrophoretic display is a display that utilizes a so-calleddielectrophoretic effect by which a substance having a high dielectricconstant moves to a high-electric field region. An electrophoreticdisplay device does not need to use a polarizing plate which is requiredin a liquid crystal display device.

A solution in which the above microcapsules are dispersed in a solventis referred to as electronic ink. This electronic ink can be printed ona surface of glass, plastic, cloth, paper, or the like. Furthermore, byusing a color filter or particles that have a pigment, color display canalso be achieved.

In addition, when a plurality of the above microcapsules are arranged asappropriate over an active matrix substrate so as to be interposedbetween two electrodes, an active matrix display device can becompleted, and display can be performed by application of an electricfield to the microcapsules. For example, the active matrix substrateobtained by the thin film transistor described in any of Embodiments 1to 8 can be used.

Note that the first particles and the second particles in themicrocapsules may each be formed of a single material selected from aconductive material, an insulating material, a semiconductor material, amagnetic material, a liquid crystal material, a ferroelectric material,an electroluminescent material, an electrochromic material, and amagnetophoretic material, or formed of a composite material of any ofthese.

FIG. 28 illustrates active matrix electronic paper as an example of asemiconductor device. A thin film transistor 581 used for thesemiconductor device can be formed in a manner similar to the thin filmtransistor described in any of Embodiments 1 to 8, which is a highlyreliable thin film transistor including an oxide semiconductor layer.

The electronic paper in FIG. 28 is an example of a display device usinga twisting ball display system. The twisting ball display system refersto a method in which spherical particles each colored in black and whiteare arranged between a first electrode layer and a second electrodelayer which are electrode layers used for a display element, and apotential difference is generated between the first electrode layer andthe second electrode layer to control orientation of the sphericalparticles, so that display is performed.

The thin film transistor 581 formed over a substrate 580 is a bottomgate thin film transistor and is covered with an insulating film 583which is in contact with a semiconductor layer. A source electrode layeror a drain electrode layer of the thin film transistor 581 is in contactwith a first electrode layer 587 in an opening formed in an insulatinglayer 585, whereby the thin film transistor 581 is electricallyconnected to the first electrode layer 587. Between the first electrodelayer 587 and a second electrode layer 588 on a substrate 596, sphericalparticles 589 are provided. Each spherical particle 589 includes a blackregion 590 a and a white region 590 b, and a cavity 594 filled withliquid around the black region 590 a and the white region 590 b. Thecircumference of the spherical particle 589 is filled with a filler 595such as a resin or the like. The first electrode layer 587 correspondsto a pixel electrode, and the second electrode layer 588 corresponds toa common electrode. The second electrode layer 588 is electricallyconnected to a common potential line provided over the same substrate580 as the thin film transistor 581. With the use of a common connectionportion, the second electrode layer 588 can be electrically connected tothe common potential line via conductive particles provided between thesubstrate 580 and the substrate 596.

Further, instead of the twisting ball, an electrophoretic element canalso be used. A microcapsule having a diameter of approximately 10 μm to200 μm in which transparent liquid, positively charged whitemicroparticles, and negatively charged black microparticles areencapsulated, is used. In the microcapsule which is provided between thefirst electrode layer and the second electrode layer, when an electricfield is applied by the first electrode layer and the second electrodelayer, the white microparticles and the black microparticles move toopposite sides, so that white or black can be displayed. A displayelement using this principle is an electrophoretic display element andis generally called electronic paper. The electrophoretic displayelement has higher reflectance than a liquid crystal display element,and thus, an auxiliary light is unnecessary, power consumption is low,and a display portion can be recognized in a dim place. In addition,even when power is not supplied to the display portion, an image whichhas been displayed once can be maintained. Accordingly, a displayedimage can be stored even if a semiconductor device having a displayfunction (which may be referred to simply as a display device or asemiconductor device provided with a display device) is distanced froman electric wave source.

Through this process, a highly reliable electronic paper as asemiconductor device can be manufactured.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 12

An example of a light-emitting display device will be described as asemiconductor device. As a display element included in a display device,a light-emitting element utilizing electroluminescence is describedhere. Light-emitting elements utilizing electroluminescence areclassified according to whether a light-emitting material is an organiccompound or an inorganic compound. In general, the former is referred toas an organic EL element, and the latter is referred to as an inorganicEL element.

In an organic EL element, by application of voltage to a light-emittingelement, electrons and holes are separately injected from a pair ofelectrodes into a layer containing a light-emitting organic compound,and current flows. The carriers (electrons and holes) are recombined,and thus the light-emitting organic compound is excited. Thelight-emitting organic compound returns to a ground state from theexcited state, thereby emitting light. Based on this mechanism, thislight-emitting element is referred to as a current-excitationlight-emitting element.

The inorganic EL elements are classified according to their elementstructures into a dispersion-type inorganic EL element and a thin-filminorganic EL element. A dispersion-type inorganic EL element has alight-emitting layer where particles of a light-emitting material aredispersed in a binder, and its light emission mechanism isdonor-acceptor recombination type light emission that utilizes a donorlevel and an acceptor level. A thin-film inorganic EL element has astructure where a light-emitting layer is sandwiched between dielectriclayers, which are further sandwiched between electrodes, and its lightemission mechanism is localized type light emission that utilizesinner-shell electron transition of metal ions. Note that an example ofan organic EL element as a light-emitting element is described here.

FIG. 29 illustrates an example of a pixel structure to which digitaltime grayscale driving can be applied, as an example of a semiconductordevice.

A structure and operation of a pixel to which digital time grayscaledriving can be applied are described. Here, one pixel includes twon-channel transistors each of which includes an oxide semiconductorlayer as a channel formation region.

A pixel 6400 includes a switching transistor 6401, a driver transistorfor a light-emitting element 6402, a light-emitting element 6404, and acapacitor 6403. A gate of the switching transistor 6401 is connected toa scan line 6406, a first electrode (one of a source electrode and adrain electrode) of the switching transistor 6401 is connected to asignal line 6405, and a second electrode (the other of the sourceelectrode and the drain electrode) of the switching transistor 6401 isconnected to a gate of the driver transistor for a light-emittingelement 6402. The gate of the driver transistor for a light-emittingelement 6402 is connected to a power supply line 6407 via the capacitor6403, a first electrode of the driver transistor for a light-emittingelement 6402 is connected to the power supply line 6407, and a secondelectrode of the driver transistor for a light-emitting element 6402 isconnected to a first electrode (a pixel electrode) of the light-emittingelement 6404. A second electrode of the light-emitting element 6404corresponds to a common electrode 6408. The common electrode 6408 iselectrically connected to a common potential line provided over the samesubstrate.

The second electrode (common electrode 6408) of the light-emittingelement 6404 is set to a low power supply potential. Note that the lowpower supply potential is a potential satisfying the low power supplypotential<a high power supply potential with reference to the high powersupply potential that is set to the power supply line 6407. As the lowpower supply potential, GND, 0 V, or the like may be employed, forexample. A potential difference between the high power supply potentialand the low power supply potential is applied to the light-emittingelement 6404 and current is supplied to the light-emitting element 6404,so that the light-emitting element 6404 emits light. Here, in order tomake the light-emitting element 6404 emit light, each potential is setso that the potential difference between the high power supply potentialand the low power supply potential is forward threshold voltage orhigher of the light-emitting element 6404.

Gate capacitance of the driver transistor for a light-emitting element6402 may be used as a substitute for the capacitor 6403, so that thecapacitor 6403 can be omitted. The gate capacitance of the drivertransistor for a light-emitting element 6402 may be formed between achannel region and a gate electrode.

In the case of a voltage-input voltage driving method, a video signal isinput to the gate of the driver transistor for a light-emitting element6402 so that the driver transistor for a light-emitting element 6402 isin either of two states of being sufficiently turned on and turned off.That is, the driver transistor for a light-emitting element 6402operates in a linear region. Since the driver transistor for alight-emitting element 6402 operates in a linear region, voltage higherthan the voltage of the power supply line 6407 is applied to the gate ofthe driver transistor for a light-emitting element 6402. Note thatvoltage higher than or equal to (voltage of the power supply line+Vth ofthe driver transistor for a light-emitting element 6402) is applied tothe signal line 6405.

In the case of performing analog grayscale driving instead of digitaltime grayscale driving, the same pixel structure as that in FIG. 29 canbe used by changing signal input.

In the case of performing analog grayscale driving, voltage higher thanor equal to (forward voltage of the light-emitting element 6404+Vth ofthe driver transistor for a light-emitting element 6402) is applied tothe gate of the driver transistor for a light-emitting element 6402. Theforward voltage of the light-emitting element 6404 indicates voltage atwhich a desired luminance is obtained, and includes at least forwardthreshold voltage. By inputting a video signal to enable the drivertransistor for a light-emitting element 6402 to operate in a saturationregion, current can be supplied to the light-emitting element 6404. Inorder to allow the driver transistor for a light-emitting element 6402to operate in the saturation region, the potential of the power supplyline 6407 is higher than a gate potential of the driver transistor for alight-emitting element 6402. When an analog video signal is used, it ispossible to feed current to the light-emitting element 6404 inaccordance with the video signal and perform analog grayscale driving.

Note that an embodiment of the present invention is not limited to thepixel structure illustrated in FIG. 29. For example, a switch, aresistor, a capacitor, a transistor, a logic circuit, or the like may beadded to the pixel illustrated in FIG. 29.

Next, structures of the light-emitting element will be described withreference to FIGS. 30A to 30C. A cross-sectional structure of a pixel isdescribed by taking an n-channel driver TFT for a light-emitting elementas an example. Driver TFTs for a light-emitting element 7001, 7011, and7021 used in semiconductor devices illustrated in FIGS. 30A, 30B, and30C, respectively, can be formed in a manner similar to that of the thinfilm transistor which is described in any of Embodiments 1 to 8 andarranged in a pixel and are highly reliable thin film transistors eachincluding an oxide semiconductor layer.

In order to extract light emitted from the light-emitting element, atleast one of an anode and a cathode is required to transmit light. Athin film transistor and a light-emitting element are formed over asubstrate. A light-emitting element can have a top emission structure,in which light emission is extracted through the surface opposite to thesubstrate; a bottom emission structure, in which light emission isextracted through the surface on the substrate side; or a dual emissionstructure, in which light emission is extracted through the surfaceopposite to the substrate and the surface on the substrate side. Thepixel structure can be applied to a light-emitting element having any ofthese emission structures.

A light-emitting element having a top emission structure will bedescribed with reference to FIG. 30A.

FIG. 30A is a cross-sectional view of a pixel in the case where thedriver TFT for a light-emitting element 7001 is of an n type and lightis emitted from a light-emitting element 7002 to an anode 7005 side. InFIG. 30A, a cathode 7003 of the light-emitting element 7002 iselectrically connected to the driver TFT for a light-emitting element7001, and a light-emitting layer 7004 and the anode 7005 are stacked inthat order over the cathode 7003. The cathode 7003 can be formed using avariety of conductive materials as long as they have a low work functionand reflect light. For example, Ca, Al, MgAg, AlLi, or the like isdesirably used. The light-emitting layer 7004 may be formed using asingle layer or a plurality of layers stacked. When the light-emittinglayer 7004 is formed using a plurality of layers, the light-emittinglayer 7004 is formed by stacking an electron-injection layer, anelectron-transport layer, a light-emitting layer, a hole-transportlayer, and a hole-injection layer in that order over the cathode 7003.It is not necessary to form all of these layers. The anode 7005 is madeof a light-transmitting conductive material such as indium oxidecontaining tungsten oxide, indium zinc oxide containing tungsten oxide,indium oxide containing titanium oxide, indium tin oxide containingtitanium oxide, indium tin oxide (hereinafter referred to as ITO),indium zinc oxide, or indium tin oxide to which silicon oxide is added.

A partition 7009 is provided so as to cover part of the cathode 7003.The partition 7009 is formed using an organic resin film of polyimide,acrylic, polyamide, epoxy, or the like, an inorganic insulating film, ororganic polysiloxane. It is particularly preferable that the partition7009 be formed using a photosensitive resin material so that a sidesurface of the partition 7009 is formed as an inclined surface withcontinuous curvature. When the partition 7009 is formed using aphotosensitive resin material, a step of forming a resist mask can beomitted.

The light-emitting element 7002 corresponds to a region where thelight-emitting layer 7004 is sandwiched between the cathode 7003 and theanode 7005. In the case of the pixel illustrated in FIG. 30A, light isemitted from the light-emitting element 7002 to the anode 7005 side asindicated by an arrow.

Next, a light-emitting element having a bottom emission structure willbe described with reference to FIG. 30B. FIG. 30B is a cross-sectionalview of a pixel in the case where the driver TFT for a light-emittingelement 7011 is an n-channel transistor and light is emitted from alight-emitting element 7012 to a cathode 7013 side. In FIG. 30B, thecathode 7013 of the light-emitting element 7012 is formed over alight-transmitting conductive film 7017 that is electrically connectedto the driver TFT for a light-emitting element 7011, and alight-emitting layer 7014 and an anode 7015 are stacked in that orderover the cathode 7013. A light-blocking film 7016 for reflecting orblocking light may be formed so as to cover the anode 7015 when theanode 7015 has a light-transmitting property. For the cathode 7013,various materials can be used as in the case of FIG. 30A as long as theyare conductive materials having a low work function. The cathode 7013 isformed to a thickness that can transmit light (preferably, approximately5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nmcan be used as the cathode 7013. Similar to the case of FIG. 30A, thelight-emitting layer 7014 may be formed using either a single layer or aplurality of layers stacked. The anode 7015 is not required to transmitlight, but can be formed using a conductive material having alight-transmitting property with respect to visible light as in the caseof FIG. 30A. As the light-blocking film 7016, a metal or the like thatreflects light can be used; however, it is not limited to a metal film.For example, a resin or the like to which black pigments are added canalso be used.

A partition 7019 is provided so as to cover part of the conductive film7017. The partition 7019 is formed using an organic resin film ofpolyimide, acrylic, polyamide, epoxy, or the like, an inorganicinsulating film, or organic polysiloxane. It is particularly preferablethat the partition 7019 be formed using a photosensitive resin materialso that a side surface of the partition 7019 is formed as an inclinedsurface with continuous curvature. When the partition 7019 is formedusing a photosensitive resin material, a step of forming a resist maskcan be omitted.

The light-emitting element 7012 corresponds to a region where thelight-emitting layer 7014 is sandwiched between the cathode 7013 and theanode 7015. In the case of the pixel illustrated in FIG. 30B, light isemitted from the light-emitting element 7012 to the cathode 7013 side asindicated by an arrow.

Next, a light-emitting element having a dual emission structure will bedescribed with reference to FIG. 30C. In FIG. 30C, a cathode 7023 of alight-emitting element 7022 is formed over a light-transmittingconductive film 7027 which is electrically connected to the driver TFTfor a light-emitting element 7021, and a light-emitting layer 7024 andan anode 7025 are sequentially stacked over the cathode 7023. For thecathode 7023, various materials can be used as in the case of FIG. 30Aas long as they are conductive materials having a low work function. Thecathode 7023 is formed to a thickness that can transmit light. Forexample, a film of Al having a thickness of 20 nm can be used as thecathode 7023. As in FIG. 30A, the light-emitting layer 7024 may beformed using either a single layer or a plurality of layers stacked. Ina manner similar to FIG. 30A, the anode 7025 can be formed using alight-transmitting conductive material.

A partition 7029 is provided so as to cover part of the conductive film7027. The partition 7029 is formed using an organic resin film ofpolyimide, acrylic, polyamide, epoxy, or the like, an inorganicinsulating film, or organic polysiloxane. It is particularly preferablethat the partition 7029 be formed using a photosensitive resin materialso that a side surface of the partition 7029 is formed as an inclinedsurface with continuous curvature. When the partition 7029 is formedusing a photosensitive resin material, a step of forming a resist maskcan be omitted.

The light-emitting element 7022 corresponds to a region where thecathode 7023, the light-emitting layer 7024, and the anode 7025 overlapone another. In the case of the pixel illustrated in FIG. 30C, light isemitted from the light-emitting element 7022 to both the anode 7025 sideand the cathode 7023 side as indicated by arrows.

Although the organic EL elements are described here as thelight-emitting elements, an inorganic EL element can also be provided asa light-emitting element.

Note that the example is described in which a thin film transistor (adriver TFT for a light-emitting element) which controls the driving of alight-emitting element is electrically connected to the light-emittingelement; however, a structure may be employed in which a TFT for currentcontrol is connected between the driver TFT for a light-emitting elementand the light-emitting element.

Note that the structure of the semiconductor device is not limited tothose illustrated in FIGS. 30A to 30C and can be modified in variousways based on techniques disclosed in this specification.

Next, the appearance and cross section of a light-emitting display panel(also referred to as a light-emitting panel) which corresponds to onemode of a semiconductor device will be described with reference to FIGS.31A and 31B. FIG. 31A is a top view of a panel in which a thin filmtransistor and a light-emitting element formed over a first substrateare sealed between the first substrate and a second substrate with asealant. FIG. 31B is a cross-sectional view taken along line H-I of FIG.31A.

A sealant 4505 is provided so as to surround a pixel portion 4502,signal line driver circuits 4503 a and 4503 b, and scan line drivercircuits 4504 a and 4504 b which are provided over a first substrate4501. In addition, a second substrate 4506 is provided over the pixelportion 4502, the signal line driver circuits 4503 a and 4503 b, and thescan line driver circuits 4504 a and 4504 b. Accordingly, the pixelportion 4502, the signal line driver circuits 4503 a and 4503 b, and thescan line driver circuits 4504 a and 4504 b are sealed together with afiller 4507, by the first substrate 4501, the sealant 4505, and thesecond substrate 4506. It is preferable that a panel be packaged(sealed) with a protective film (such as a laminate film or anultraviolet curable resin film) or a cover material with highair-tightness and little degasification so that the panel is not exposedto the outside air, in this manner.

The pixel portion 4502, the signal line driver circuits 4503 a and 4503b, and the scan line driver circuits 4504 a and 4504 b formed over thefirst substrate 4501 each include a plurality of thin film transistors,and a thin film transistor 4510 included in the pixel portion 4502 and athin film transistor 4509 included in the signal line driver circuit4503 a are illustrated as an example in FIG. 31B.

For the thin film transistors 4509 and 4510, the highly reliable thinfilm transistor including the oxide semiconductor layer described in anyof Embodiments 1 to 8 can be employed. The thin film transistors 4509and 4510 are n-channel thin film transistors.

Moreover, reference numeral 4511 denotes a light-emitting element. Afirst electrode layer 4517 which is a pixel electrode included in thelight-emitting element 4511 is electrically connected to a sourceelectrode layer or a drain electrode layer of the thin film transistor4510. Note that the structure of the light-emitting element 4511 is, butnot limited to, the stacked structure which includes the first electrodelayer 4517, an electroluminescent layer 4512, and a second electrodelayer 4513. The structure of the light-emitting element 4511 can bechanged as appropriate depending on the direction in which light isextracted from the light-emitting element 4511, or the like.

A partition 4520 is formed using an organic resin film, an inorganicinsulating film, or organic polysiloxane. It is particularly preferablethat the partition 4520 be formed using a photosensitive material and anopening be formed over the first electrode layer 4517 so that a sidewallof the opening is formed as an inclined surface with continuouscurvature.

The electroluminescent layer 4512 may be formed with a single layer or aplurality of layers stacked.

A protective film may be formed over the second electrode layer 4513 andthe partition 4520 in order to prevent entry of oxygen, hydrogen,moisture, carbon dioxide, and the like into the light-emitting element4511. As the protective film, a silicon nitride film, a silicon nitrideoxide film, a DLC film, or the like can be formed.

In addition, a variety of signals and potentials are supplied to thesignal line driver circuits 4503 a and 4503 b, the scan line drivercircuits 4504 a and 4504 b, or the pixel portion 4502 from FPCs 4518 aand 4518 b.

A connection terminal electrode 4515 is formed using the same conductivefilm as the first electrode layer 4517 included in the light-emittingelement 4511, and a terminal electrode 4516 is formed using the sameconductive film as the source and drain electrode layers included in thethin film transistor 4509.

The connection terminal electrode 4515 is electrically connected to aterminal included in the FPC 4518 a via an anisotropic conductive film4519.

As the second substrate 4506 located in the direction in which light isextracted from the light-emitting element 4511 needs to have alight-transmitting property. In that case, a light-transmitting materialsuch as a glass plate, a plastic plate, a polyester film, or an acrylicfilm is used for the second substrate 4506.

As the filler 4507, an ultraviolet curable resin or a thermosettingresin can be used, in addition to an inert gas such as nitrogen orargon. For example, polyvinyl chloride (PVC), acrylic, polyimide, anepoxy resin, a silicone resin, polyvinyl butyral (PVB), or ethylenevinyl acetate (EVA) can be used. For example, nitrogen may be used forthe filler 4507.

In addition, if needed, an optical film, such as a polarizing plate, acircularly polarizing plate (including an elliptically polarizingplate), a retardation plate (a quarter-wave plate or a half-wave plate),or a color filter, may be provided as appropriate on a light-emittingsurface of the light-emitting element. Further, the polarizing plate orthe circularly polarizing plate may be provided with an anti-reflectionfilm. For example, anti-glare treatment by which reflected light can bediffused by projections and depressions on the surface so as to reducethe glare can be performed.

The signal line driver circuits 4503 a and 4503 b and the scan linedriver circuits 4504 a and 4504 b may be mounted as driver circuitsformed using a single crystal semiconductor film or a polycrystallinesemiconductor film over a substrate separately prepared. Alternatively,only the signal line driver circuits or part thereof, or only the scanline driver circuits or part thereof may be separately formed andmounted. This embodiment is not limited to the structure illustrated inFIGS. 31A and 31B.

Through this process, a highly reliable light-emitting display device(display panel) as a semiconductor device can be manufactured.

This embodiment can be implemented in appropriate combination with thestructures described in the other embodiments.

Embodiment 13

A semiconductor device disclosed in this specification can be applied toelectronic paper. Electronic paper can be used for electronic devices ofa variety of fields as long as they can display data. For example,electronic paper can be applied to an e-book reader (electronic book), aposter, an advertisement in a vehicle such as a train, or displays ofvarious cards such as a credit card. An example of the electronic deviceis illustrated in FIG. 32.

FIG. 32 illustrates an example of an e-book reader 2700. For example,the e-book reader 2700 includes two housings, a housing 2701 and ahousing 2703. The housing 2701 and the housing 2703 are combined with ahinge 2711 so that the e-book reader 2700 can be opened and closed withthe hinge 2711 as an axis. With such a structure, the e-book reader 2700can operate like a paper book.

A display portion 2705 and a display portion 2707 are incorporated inthe housing 2701 and the housing 2703, respectively. The display portion2705 and the display portion 2707 may display one image or differentimages. In the case where the display portion 2705 and the displayportion 2707 display different images, for example, a display portion onthe right side (the display portion 2705 in FIG. 32) can display textand a display portion on the left side (the display portion 2707 in FIG.32) can display graphics.

FIG. 32 illustrates an example in which the housing 2701 is providedwith an operation portion and the like. For example, the housing 2701 isprovided with a power switch 2721, an operation key 2723, a speaker2725, and the like. With the operation key 2723, pages can be turned.Note that a keyboard, a pointing device, and the like may be provided onthe same surface as the display portion of the housing. Furthermore, anexternal connection terminal (an earphone terminal, a USB terminal, aterminal that can be connected to various cables such as an AC adapterand a USB cable, or the like), a recording medium insertion portion, andthe like may be provided on the back surface or the side surface of thehousing. Moreover, the e-book reader 2700 may have a function of anelectronic dictionary.

The e-book reader 2700 may have a structure capable of wirelesslytransmitting and receiving data. Through wireless communication, desiredbook data or the like can be purchased and downloaded from an electronicbook server.

Embodiment 14

A semiconductor device disclosed in this specification can be applied toa variety of electronic devices (including game machines). Examples ofelectronic devices are a television set (also referred to as atelevision or a television receiver), a monitor of a computer or thelike, a camera such as a digital camera or a digital video camera, adigital photo frame, a cellular phone handset (also referred to as acellular phone or a cellular phone device), a portable game console, aportable information terminal, an audio reproducing device, alarge-sized game machine such as a pachinko machine, and the like.

FIG. 33A illustrates an example of a television set 9600. In thetelevision set 9600, a display portion 9603 is incorporated in a housing9601. The display portion 9603 can display images. Here, the housing9601 is supported by a stand 9605.

The television set 9600 can be operated with an operation switch of thehousing 9601 or a separate remote controller 9610. Channels and volumecan be controlled with an operation key 9609 of the remote controller9610 so that an image displayed on the display portion 9603 can becontrolled. Furthermore, the remote controller 9610 may be provided witha display portion 9607 for displaying data output from the remotecontroller 9610.

Note that the television set 9600 is provided with a receiver, a modem,and the like. With the use of the receiver, general televisionbroadcasting can be received. Moreover, when the display device isconnected to a communication network with or without wires via themodem, one-way (from a sender to a receiver) or two-way (between asender and a receiver or between receivers) information communicationcan be performed.

FIG. 33B illustrates an example of a digital photo frame 9700. Forexample, in the digital photo frame 9700, a display portion 9703 isincorporated in a housing 9701. The display portion 9703 can display avariety of images. For example, the display portion 9703 can displaydata of an image taken with a digital camera or the like and function asa normal photo frame.

Note that the digital photo frame 9700 is provided with an operationportion, an external connection portion (a USB terminal, a terminal thatcan be connected to various cables such as a USB cable, or the like), arecording medium insertion portion, and the like. Although thesecomponents may be provided on the surface on which the display portionis provided, it is preferable to provide them on the side surface or theback surface for the design of the digital photo frame 9700. Forexample, a memory storing data of an image taken with a digital camerais inserted in the recording medium insertion portion of the digitalphoto frame, whereby the image data can be transferred and thendisplayed on the display portion 9703.

The digital photo frame 9700 may be configured to transmit and receivedata wirelessly. The structure may be employed in which desired imagedata is transferred wirelessly to be displayed.

FIG. 34A is a portable amusement machine including two housings, ahousing 9881 and a housing 9891. The housings 9881 and 9891 areconnected with a connection portion 9893 so as to be opened and closed.A display portion 9882 and a display portion 9883 are incorporated inthe housing 9881 and the housing 9891, respectively. In addition, theportable amusement machine illustrated in FIG. 34A includes a speakerportion 9884, a recording medium insert portion 9886, an LED lamp 9890,an input means (an operation key 9885, a connection terminal 9887, asensor 9888 (a sensor having a function of measuring force,displacement, position, speed, acceleration, angular velocity,rotational frequency, distance, light, liquid, magnetism, temperature,chemical substance, sound, time, hardness, electric field, current,voltage, electric power, radiation, flow rate, humidity, gradient,oscillation, odor, or infrared rays), or a microphone 9889), and thelike. It is needless to say that the structure of the portable amusementmachine is not limited to the above and other structures provided withat least a semiconductor device disclosed in this specification can beemployed. The portable amusement machine may include other accessoryequipment, as appropriate. The portable amusement machine illustrated inFIG. 34A has a function of reading a program or data stored in arecording medium to display it on the display portion, and a function ofsharing information with another portable amusement machine by wirelesscommunication. The portable amusement machine illustrated in FIG. 34Acan have various functions without limitation to the above.

FIG. 34B illustrates an example of a slot machine 9900 which is anamusement machine with a big size. In the slot machine 9900, a displayportion 9903 is incorporated in a housing 9901. In addition, the slotmachine 9900 includes an operation means such as a start lever or a stopswitch, a coin slot, a speaker, and the like. It is needless to say thatthe structure of the slot machine 9900 is not limited to the above andother structures provided with at least a semiconductor device disclosedin this specification may be employed. The slot machine 9900 may includeother accessory equipment, as appropriate.

FIG. 35A is a perspective view illustrating an example of a portablecomputer.

In the portable computer of FIG. 35A, a top housing 9301 having adisplay portion 9303 and a bottom housing 9302 having a keyboard 9304can overlap each other by closing a hinge unit which connects the tophousing 9301 and the bottom housing 9302. The portable computer of FIG.35A can be convenient for carrying, and in the case of using thekeyboard for input, the hinge unit is opened and the user can inputlooking at the display portion 9303.

The bottom housing 9302 includes a pointing device 9306 with which inputcan be performed, in addition to the keyboard 9304. Further, when thedisplay portion 9303 is a touch input panel, input can be performed bytouching part of the display portion. The bottom housing 9302 includesan arithmetic function portion such as a CPU or hard disk. In addition,the bottom housing 9302 includes another device, for example, anexternal connection port 9305 into which a communication cableconformable to communication standards of a USB is inserted.

The top housing 9301, which includes a display portion 9307 and can keepthe display portion 9307 therein by sliding it toward the inside of thetop housing 9301, can have a large display screen. In addition, the usercan adjust the orientation of a screen of the display portion 9307 whichcan be kept in the top housing 9301. When the display portion 9307 whichcan be kept in the top housing 9301 is a touch input panel, input can beperformed by touching part of the display portion 9307 which can be keptin the top housing 9301.

The display portion 9303 or the display portion 9307 which can be keptin the top housing 9301 are formed using an image display device of aliquid crystal display panel, a light-emitting display panel such as anorganic light-emitting element or an inorganic light-emitting element,or the like.

In addition, the portable computer in FIG. 35A can be provided with areceiver and the like and can receive a television broadcast to displayan image on the display portion. The user can watch a televisionbroadcast when the whole screen of the display portion 9307 is exposedby sliding the display portion 9307 while the hinge unit which connectsthe top housing 9301 and the bottom housing 9302 is kept closed. In thiscase, the hinge unit is not opened and display is not performed on thedisplay portion 9303. In addition, start up of only a circuit fordisplaying a television broadcast is performed. Therefore, power can beconsumed to the minimum, which is useful for the portable computer whosebattery capacity is limited.

FIG. 35B is a perspective view illustrating an example of a cellularphone that the user can wear on the wrist like a wristwatch.

This cellular phone is formed including a main body which includes acommunication device having at least a telephone function, and abattery; a band portion 9204 which enables the main body to be worn onthe wrist; an adjusting portion 9205 for adjusting the band portion tofit the wrist; a display portion 9201; a speaker 9207; and a microphone9208.

In addition, the main body includes operation switches 9203. Theoperation switches 9203 can serve, for example, as a switch for startinga program for the Internet when pushed, in addition to serving as apower switch, a switch for shifting the display, a switch forinstruction to start taking images, or the like, and can be configuredto have respective functions.

Input to this cellular phone is operated by touching the display portion9201 with a finger or an input pen, operating the operation switches9203, or inputting voice into the microphone 9208. In FIG. 35B, displaybuttons 9202 are displayed on the display portion 9201. Input can beperformed by touching the display buttons 9202 with a finger or thelike.

Further, the main body includes a camera portion 9206 including an imagepick-up means having a function of converting an image of an object,which is formed through a camera lens, to an electronic image signal.Note that the camera portion is not necessarily provided.

The cellular phone illustrated in FIG. 35B is provided with a receiverof a television broadcast and the like, and can display an image on thedisplay portion 9201 by receiving a television broadcast. In addition,the cellular phone illustrated in FIG. 35B is provided with a memorydevice and the like such as a memory, and can record a televisionbroadcast in the memory. The cellular phone illustrated in FIG. 35B mayhave a function of collecting location information such as GPS.

An image display device of a liquid crystal display panel, alight-emitting display panel such as an organic light-emitting elementor an inorganic light-emitting element, or the like is used as thedisplay portion 9201. The cellular phone illustrated in FIG. 35B iscompact and lightweight and thus has limited battery capacity.Therefore, a panel which can be driven with low power consumption ispreferably used as a display device for the display portion 9201.

Note that FIG. 35B illustrates the electronic device which is worn onthe wrist; however, this embodiment is not limited thereto as long as aportable shape is employed.

This application is based on Japanese Patent Application serial No.2009-164197 filed with Japan Patent Office on Jul. 10, 2009, the entirecontents of which are hereby incorporated by reference.

1. (canceled)
 2. A semiconductor device comprising: a gate electrode layer over a substrate; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a crystalline film over the oxide semiconductor layer, the crystalline film comprising zinc and oxygen; a source electrode layer over the crystalline film, the source electrode layer being in contact with a side surface of the oxide semiconductor layer and a side surface of the crystalline film; and an insulating film over the source electrode layer.
 3. The semiconductor device according to claim 2, wherein the oxide semiconductor layer comprises a nanocrystal.
 4. The semiconductor device according to claim 2, wherein the oxide semiconductor layer comprises a crystal having a diameter of 1 nm to 10 nm.
 5. The semiconductor device according to claim 2, wherein the crystalline film is a polycrystalline film.
 6. The semiconductor device according to claim 2, wherein the crystalline film is a microcrystalline film.
 7. The semiconductor device according to claim 2, wherein a resistance of the crystalline film is lower than a resistance of the oxide semiconductor layer.
 8. The semiconductor device according to claim 2, further comprising a gate wiring over the insulating film, wherein the gate wiring is electrically connected to the gate electrode layer.
 9. The semiconductor device according to claim 8, further comprising: a connection electrode layer over the gate insulating layer; and a source wiring over the insulating film, wherein the gate wiring is electrically connected to the connection electrode layer, and wherein the source wiring overlaps the connection electrode layer.
 10. The semiconductor device according to claim 8, further comprising: a connection electrode layer over the gate insulating layer; and a source wiring over the insulating film, wherein the source wiring is electrically connected to the connection electrode layer, and wherein the gate wiring overlaps the connection electrode layer.
 11. The semiconductor device according to claim 8, wherein the gate wiring overlaps the source electrode layer.
 12. An electronic device comprising: a battery; and a display portion comprising: a gate electrode layer over a substrate; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a crystalline film over the oxide semiconductor layer, the crystalline film comprising zinc and oxygen; a source electrode layer over the crystalline film, the source electrode layer being in contact with a side surface of the oxide semiconductor layer and a side surface of the crystalline film; and an insulating film over the source electrode layer.
 13. The electronic device according to claim 12, wherein the oxide semiconductor layer comprises a nanocrystal.
 14. The electronic device according to claim 12, wherein the oxide semiconductor layer comprises a crystal having a diameter of 1 nm to 10 nm.
 15. The electronic device according to claim 12, wherein the crystalline film is a polycrystalline film.
 16. The electronic device according to claim 12, wherein the crystalline film is a microcrystalline film.
 17. The electronic device according to claim 12, wherein a resistance of the crystalline film is lower than a resistance of the oxide semiconductor layer.
 18. The electronic device according to claim 12, wherein the display portion further comprises a gate wiring over the insulating film, and wherein the gate wiring is electrically connected to the gate electrode layer.
 19. The electronic device according to claim 18, wherein the display portion further comprises: a connection electrode layer over the gate insulating layer; and a source wiring over the insulating film, wherein the gate wiring is electrically connected to the connection electrode layer, and wherein the source wiring overlaps the connection electrode layer.
 20. The electronic device according to claim 18, wherein the display portion further comprises: a connection electrode layer over the gate insulating layer; and a source wiring over the insulating film, wherein the source wiring is electrically connected to the connection electrode layer, and wherein the gate wiring overlaps the connection electrode layer.
 21. The electronic device according to claim 18, wherein the gate wiring overlaps the source electrode layer. 